4. Capacitance measured for initial qualification or design changes which may affect the value. VDDIDDVDDVVDDDDRSTP0EA(NC)XTAL2CLOCKXTAL1SIGNALVSSGNDtCLCH = tCHCL = 5nsFigure 4. IDD Test Condition, Active ModeAll other pinsdisconnectedVDD -0.50.7 VDDtCHCX0.45V0.2 VDD -0.1tCHCXtCLCHtCHCLtCLCLFigure 5. Clock Signal Waveform for IDD Tests in Active and Idle ModestCLCH = tCHCL = 5ns 9