Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 3

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ADSP-21362/ADSP-21363/ADSP-2 1364/ADSP-21365/ADSP-21366 GENERAL DESCRIPTION
The ADSP-2136x SHARC® processor is a member of the SIMD Table 1 shows performance benchmarks for these devices. SHARC family of DSPs that feature Analog Devices, Inc., Super Table 2 shows the features of the individual product offerings. Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with
Table 1. Benchmarks (at 333 MHz)
first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are
Speed
32-/40-bit floating-point processors optimized for high
Benchmark Algorithm (at 333 MHz)
performance automotive audio applications. They contain a 1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs large on-chip SRAM and ROM, multiple internal buses to elim- FIR Filter (per tap)1 1.5 ns inate I/O bottlenecks, and an innovative digital audio interface IIR Filter (per biquad)1 6.0 ns (DAI). Matrix Multiply (pipelined) As shown in the functional block diagram on Page 1, the [3×3] × [3×1] 13.5 ns ADSP-2136x uses two computational units to deliver a signifi- [4×4] × [4×1] 23.9 ns cant performance increase over the previous SHARC processors Divide (y/x) 10.5 ns on a range of signal processing algorithms. With its SIMD com- Inverse Square Root 16.3 ns putational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. 1 Assumes two files in multichannel SIMD mode.
Table 2. ADSP-2136x Family Features Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366
RAM 3M bit 3M bit 3M bit 3M bit 3M bit ROM 4M bit 4M bit 4M bit 4M bit 4M bit Audio Decoders in ROM1 No No No Yes Yes Pulse-Width Modulation Yes Yes Yes Yes Yes S/PDIF Yes No Yes Yes Yes DTCP2 Yes No No Yes No SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB 1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. The diagram on Page 1 shows the two clock domains that make The diagram on Page 1 also shows the following architectural up the ADSP-2136x processors. The core clock domain contains features: the following features: • I/O processor that handles 32-bit DMA for the peripherals • Two processing elements, each of which comprises an • Six full duplex serial ports ALU, multiplier, shifter, and data register file • Two SPI-compatible interface ports—primary on dedi- • Data address generators (DAG1, DAG2) cated pins, secondary on DAI pins • Program sequencer with instruction cache • 8-bit or 16-bit parallel port that supports interfaces to off- • PM and DM buses capable of supporting four 32-bit data chip memory peripherals transfers between memory and the core at every core pro- • Digital audio interface that includes two precision clock cessor cycle generators (PCG), an input data port with eight serial inter- • One periodic interval timer with pinout faces (IDP), an S/PDIF receiver/transmitter, 8-channel • On-chip SRAM (3M bit) asynchronous sample rate converter (ASRC), DTCP cipher, six serial ports, a 20-bit parallel input data port • On-chip mask-programmable ROM (4M bit) (PDAP), 10 interrupts, six flag outputs, six flag inputs, • JTAG test access port for emulation and boundary scan. three timers, and a flexible signal routing unit (SRU) The JTAG provides software debug through user break- points, which allow flexible exception handling. Rev. J | Page 3 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide