Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | SHARC Processors |
| Páginas / Página | 60 / 2 — ADSP-21362/ADSP-21363/ADSP. -21364/ADSP-21365/ADSP-21366. TABLE OF … |
| Revisión | J |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
ADSP-21362/ADSP-21363/ADSP. -21364/ADSP-21365/ADSP-21366. TABLE OF CONTENTS. REVISION HISTORY. 7/13—Revision I to Revision J
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ADSP-21362/ADSP-21363/ADSP -21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS
Summary ... 1 ESD Caution .. 16 Dedicated Audio Components .. 1 Maximum Power Dissipation ... 16 General Description ... 3 Absolute Maximum Ratings ... 16 SHARC Family Core Architecture .. 4 Timing Specifications ... 16 Family Peripheral Architecture .. 6 Output Drive Currents ... 46 I/O Processor Features ... 8 Test Conditions .. 46 System Design .. 8 Capacitive Loading .. 46 Development Tools ... 9 Thermal Characteristics .. 47 Additional Information .. 10 144-Lead LQFP_EP Pin Configurations ... 48 Related Signal Chains .. 10 136-Ball BGA Pin Configurations ... 50 Pin Function Descriptions ... 11 Package Dimensions ... 53 Specifications .. 14 Surface-Mount Design .. 54 Operating Conditions .. 14 Automotive Products .. 55 Electrical Characteristics ... 15 Ordering Guide ... 56 Package Information ... 16
REVISION HISTORY 7/13—Revision I to Revision J
Updated Development Tools ...9 Added Nominal Value column in Operating Conditions .. 14 Changed Max values in Table 30 in Pulse-Width Modulation Generators .. 35 Updated Ordering Guide .. 56 Rev. J | Page 2 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21362/ADSP-21363/ADSP -21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS
Summary ... 1 ESD Caution .. 16 Dedicated Audio Components .. 1 Maximum Power Dissipation ... 16 General Description ... 3 Absolute Maximum Ratings ... 16 SHARC Family Core Architecture .. 4 Timing Specifications ... 16 Family Peripheral Architecture .. 6 Output Drive Currents ... 46 I/O Processor Features ... 8 Test Conditions .. 46 System Design .. 8 Capacitive Loading .. 46 Development Tools ... 9 Thermal Characteristics .. 47 Additional Information .. 10 144-Lead LQFP_EP Pin Configurations ... 48 Related Signal Chains .. 10 136-Ball BGA Pin Configurations ... 50 Pin Function Descriptions ... 11 Package Dimensions ... 53 Specifications .. 14 Surface-Mount Design .. 54 Operating Conditions .. 14 Automotive Products .. 55 Electrical Characteristics ... 15 Ordering Guide ... 56 Package Information ... 16
REVISION HISTORY 7/13—Revision I to Revision J
Updated Development Tools ...9 Added Nominal Value column in Operating Conditions .. 14 Changed Max values in Table 30 in Pulse-Width Modulation Generators .. 35 Updated Ordering Guide .. 56 Rev. J | Page 2 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide