Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 4

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ADSP-21362/ADSP-21363/ADSP -21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE
Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in The ADSP-2136x is code-compatible at the assembly level with SIMD mode, twice the data bandwidth is required to sustain the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the computational operation in the processing elements. Because of first generation ADSP-2106x SHARC processors. The this requirement, entering SIMD mode also doubles the ADSP-2136x shares architectural features with the ADSP-2126x bandwidth between memory and the processing elements. and ADSP-2116x SIMD SHARC processors, as shown in When using the DAGs to transfer data in SIMD mode, two data Figure 2 and detailed in the following sections. values are transferred with each access of memory or
SIMD Computational Engine
the register file. The processor contains two computational processing elements
Independent, Parallel Computation Units
that operate as a single-instruction, multiple-data (SIMD) Within each processing element is a set of computational units. engine. The processing elements are referred to as PEX and PEY The computational units consist of an arithmetic/logic unit and each contains an ALU, multiplier, shifter, and register file. (ALU), multiplier, and shifter. These units perform all opera- PEX is always active, and PEY can be enabled by setting the tions in a single cycle. The three units within each processing PEYEN mode bit in the MODE1 register. When this mode is element are arranged in parallel, maximizing computational enabled, the same instruction is executed in both processing ele- throughput. Single multifunction instructions execute parallel ments, but each processing element operates on different data. ALU and multiplier operations. In SIMD mode, the parallel This architecture is efficient at executing math intensive signal ALU and multiplier operations occur in both processing processing algorithms. elements. These computation units support IEEE 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. S
JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16x32 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX DM DATA 64 64-BIT RF DATA RF SWAP MULTIPLIER SHIFTER ALU Rx/Fx Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16x40-BIT 16x40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy
Figure 2. SHARC Core Block Diagram Rev. J | Page 4 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide