Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 10

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ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549 Host DMA Port Interface
wake up the ADSP-BF54x processors from deep sleep mode, and it can wake up the on-chip internal voltage regulator from The host DMA port (HOSTDP) facilitates a host device external the hibernate state. to the ADSP-BF54x Blackfin processors to be a DMA master and transfer data back and forth. The host device always masters Connect RTC pins RTXI and RTXO with external components the transactions, and the processor is always a DMA slave as shown in Figure 4. device. The HOSTDP is enabled through the peripheral access bus. Once the port has been enabled, the transactions are controlled
RTXI RTXO
by the external host. The external host programs standard DMA
R1
configuration words in order to send/receive data to any valid internal or external memory location. The host DMA port con-
X1
troller includes the following features:
C1 C2
• Allows an external master to configure DMA read/write data transfers and read port status • Uses a flexible asynchronous memory protocol for its external interface
SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
• Allows an 8- or 16-bit external data interface to the host
C1 = 22 pF C2 = 22 pF
device
R1 = 10 M
Ω
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
• Supports half-duplex operation
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
• Supports little/big endian data transfers • Acknowledge mode allows flow control on host Figure 4. External Components for RTC transactions • Interrupt mode guarantees a burst of FIFO depth host
WATCHDOG TIMER
transactions The ADSP-BF54x processors include a 32-bit timer that can be
REAL-TIME CLOCK
used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the proces- The ADSP-BF54x Blackfin processors’ real-time clock (RTC) sor to a known state through generation of a hardware reset, provides a robust set of digital watch features, including current non-maskable interrupt (NMI), or general-purpose interrupt if time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz the timer expires before being reset by software. The program- crystal external to the ADSP-BF54x Blackfin processors. The mer initializes the count value of the timer, enables the RTC peripheral has dedicated power supply pins so that it can appropriate interrupt, and then enables the timer. Thereafter, remain powered up and clocked even when the rest of the pro- the software must reload the counter before it counts to zero cessor is in a low-power state. The RTC provides several from the programmed value. This protects the system from programmable interrupt options, including interrupt per sec- remaining in an unknown state where software, which would ond, minute, hour, or day clock ticks, interrupt on normally reset the timer, has stopped running due to an external programmable stopwatch countdown, or interrupt at a pro- noise condition or software error. grammed alarm time. If configured to generate a hardware reset, the watchdog timer The 32.768 kHz input clock frequency is divided down to a 1 Hz resets both the core and the ADSP-BF54x processors’ peripher- signal by a prescaler. The counter function of the timer consists als. After a reset, software can determine if the watchdog was the of four counters: a 60-second counter, a 60-minute counter, a source of the hardware reset by interrogating a status bit in the 24-hour counter, and a 32,768-day counter. watchdog timer control register. When enabled, the alarm function generates an interrupt when The timer is clocked by the system clock (SCLK) at a maximum the output of the timer matches the programmed value in the frequency of f alarm control register. There are two alarms. The first alarm is SCLK. for a time of day. The second alarm is for a day and time of
TIMERS
that day. There are up to two timer units in the ADSP-BF54x Blackfin The stopwatch function counts down from a programmed value processors. One unit provides eight general-purpose program- with one-second resolution. When the stopwatch is enabled and mable timers, and the other unit provides three. Each timer has the counter underflows, an interrupt is generated. an external pin that can be configured either as a pulse width Like the other peripherals, the RTC can wake up the modulator (PWM) or timer output, as an input to clock the ADSP-BF54x processor from sleep mode upon generation of timer, or as a mechanism for measuring pulse widths and peri- any RTC wakeup event. Additionally, an RTC wakeup event can ods of external events. These timers can be synchronized to an external clock input on the TMRx pins, an external clock TMRCLK input pin, or to the internal SCLK. Rev. E | Page 10 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide