Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices)

Blackfin Embedded Processor ADSP-BF542 /ADSP-BF544 /ADSP-BF547/ ADSP-BF548 /ADSP-BF549 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor High speed USB On-the-Go (OTG) with integrated PHY Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs SD/SDIO controller RISC-like register and instruction model ATA/ATAPI-6 controller Wide range of operating voltages and flexible booting Up to 4 synchronous serial ports (SPORTs) options Up to 3 serial peripheral interfaces (SPI-compatible) Programmable on-chip voltage regulator Up to 4 UARTs, two with automatic H/W flow control 400-ball CSP_BGA, RoHS compliant package Up to 2 CAN (controller area network) 2.0B interfaces MEMORY Up to 2 TWI (2-wire interface) controllers 8- or 16-bit asynchronous host DMA interface Up to 324K bytes of on-chip memory comprised of Multiple enhanced parallel peripheral interfaces (EPPIs), instruction SRAM/cache; dedicated instruction SRAM; data supporting ITU-R BT.656 video formats and 18-/24-bit LCD SRAM/cache; dedicated data SRAM; scratchpad SRAM connections External sync memory controller supporting either DDR Media transceiver (MXVR) for connection to a MOST network SDRAM or mobile DDR SDRAM Pixel compositor for overlays, alpha blending, and color External async memory controller supporting 8-/16-bit async conversion memories and burst flash devices Up to eleven 32-bit timers/counters with PWM support NAND flash controller Real-time clock (RTC) and watchdog timer 4 memory-to-memory DMA pairs, 2 with ext. requests Up/down counter with support for rotary encoder Memory management unit providing memory protection Up to 152 general-purpose I/O (GPIOs) Code security with Lockbox secure technology and 128-bit AES/ARC4 data encryption On-chip PLL capable of frequency multiplication One-time-programmable (OTP) memory Debug/JTAG interface CAN (0-1) VOLTAGE JTAG TEST AND WATCHDOG RTC OTP REGULATOR EMULATION TIMER TWI (0-1) HOST DMA PAB 16 TIMERS(0-10) INTERRUPTS
B
UART (0-1) TS COUNTER POR UART (2-3) L2 L1 L1 L1 KEYPAD SRAM INSTR ROM INSTR SRAM DATA SRAM SPI (0-1) TS SPI (2) MXVR 32-BIT DMA POR DAB1 32 DCB 32 EAB 64 DEB 32 SPORT (2-3) USB 16-BIT DMA SPORT (0-1) DAB0 16 EXTERNAL PORT BOOT ROM NOR, DDR, MDDR SD / SDIO ATAPI EPPI (0-2) DDR/MDDR ASYNC 16 16 NAND FLASH PIXEL CONTROLLER COMPOSITOR
Figure 1. ADSP-BF549 Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide