Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 8

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ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549
The controller provides support for five different types of
Table 3. Core Event Controller (CEC)
events:
Priority
• Emulation. An emulation event causes the processor to
(0 is Highest) Event Class EVT Entry
enter emulation mode, allowing command and control of the processor via the JTAG interface. 0 Emulation/Test Control EMU 1 Reset RST • Reset. This event resets the processor. 2 Nonmaskable Interrupt NMI • Non-maskable interrupt (NMI). The NMI event can be 3 Exception EVX generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently 4 Reserved — used as a power-down indicator to initiate an orderly shut- 5 Hardware Error IVHW down of the system. 6 Core Timer IVTMR • Exceptions. Events that occur synchronously to program 7 General Interrupt 7 IVG7 flow (that is, the exception is taken before the instruction is 8 General Interrupt 8 IVG8 allowed to complete). Conditions such as data alignment 9 General Interrupt 9 IVG9 violations and undefined instructions cause exceptions. 10 General Interrupt 10 IVG10 • Interrupts. Events that occur asynchronously to program 11 General Interrupt 11 IVG11 flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 Each event type has an associated register to hold the return address and an associated return-from-event instruction. When 14 General Interrupt 14 IVG14 an event is triggered, the state of the processor is saved on the 15 General Interrupt 15 IVG15 supervisor stack.
Event Control
The ADSP-BF54x Blackfin processor event controller consists of two stages, the core event controller (CEC) and the system The ADSP-BF54x Blackfin processors provide the user with a interrupt controller (SIC). The core event controller works with very flexible mechanism to control the processing of events. In the system interrupt controller to prioritize and control all sys- the CEC, three registers are used to coordinate and control tem events. Conceptually, interrupts from the peripherals enter events. Each register is 16 bits wide: into the SIC and are then routed directly into the general-pur- • CEC interrupt latch register (ILAT). The ILAT register pose interrupts of the CEC. indicates when events have been latched. The appropriate
Core Event Controller (CEC)
bit is set when the processor has latched the event and cleared when the event has been accepted into the system. The CEC supports nine general-purpose interrupts (IVG15–7), This register is updated automatically by the controller, but in addition to the dedicated interrupt and exception events. Of it may be written only when its corresponding IMASK bit these general-purpose interrupts, the two lowest-priority inter- is cleared. rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to • CEC interrupt mask register (IMASK). The IMASK regis- support the peripherals of the ADSP-BF54x Blackfin processors. ter controls the masking and unmasking of individual Table 3 describes the inputs to the CEC, identifies their names events. When a bit is set in the IMASK register, that event is in the event vector table (EVT), and lists their priorities. unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, prevent-
System Interrupt Controller (SIC)
ing the processor from servicing the event even though the event may be latched in the ILAT register. This register The system interrupt controller provides the mapping and rout- may be read or written while in supervisor mode. Note that ing of events from the many peripheral interrupt sources to the general-purpose interrupts can be globally enabled and dis- prioritized general-purpose interrupt inputs of the CEC. abled with the STI and CLI instructions, respectively. Although the ADSP-BF54x Blackfin processors provide a default mapping, the user can alter the mappings and priorities • CEC interrupt pending register (IPEND). The IPEND reg- of interrupt events by writing the appropriate values into the ister keeps track of all nested events. A set bit in the IPEND interrupt assignment registers (SIC_IARx). The ADSP-BF54x register indicates that the event is currently active or nested Hardware Reference Manual, “System Interrupts” chapter at some level. This register is updated automatically by the describes the inputs into the SIC and the default mappings into controller but may be read while in supervisor mode. the CEC. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in the ADSP-BF54x Hardware Reference Manual, “System Interrupts” chapter. Rev. E | Page 8 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide