Datasheet ADP5054 (Analog Devices) - 10

ADP5054 Data Sheet Pin No. Mnemonic Description
39 EN1 Enable Input for Channel 1. Use an external resistor divider to set the turn-on threshold. 40 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground. 41 FB1 Feedback Sensing Input for Channel 1. 42 RT Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 2 MHz. 43 VDD Output of the Internal 3.3 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground. 44 SYNC/MODE Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 250 kHz to 2.0 MHz. This pin can also be configured as a synchronization output via the CFG34 pin configuration. Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel works in forced PWM or automatic PWM/PSM mode. When this pin is logic low, all channels operate in automatic PWM/PSM mode. 45 VREG Output of the Internal 5.0 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground. 46 FB3 Feedback Sensing Input for Channel 3. 47 COMP3 Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground. 48 EN3 Enable Input for Channel 3. Use an external resistor divider to set the turn-on threshold. 49 EPAD Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. E | Page 10 of 31 Document Outline Features Applications Typical Application Circuit General Description Revision History Detailed Functional Block Diagram Specifications Buck Regulator Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Buck Regulator Operational Modes PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes Adjustable and Fixed Output Voltage Internal Regulators (VREG and VDD) Separate Supply Applications Low-Side Device Selection Bootstrap Circuitry Active Output Discharge Switch Precision Enabling Oscillator Phase Shift Synchronization Input/Output Soft Start Parallel Operation Startup with Precharged Output Current-Limit Protection Frequency Foldback Pulse Skip in Maximum Duty Short-Circuit Protection (SCP) Latch-Off Protection Short-Circuit Latch-Off Mode Undervoltage Lockout (UVLO) Power-Good Function Thermal Shutdown Applications Information ADIsimPower Design Tool Programming the Output Voltage Voltage Conversion Limitations Current-Limit Setting Soft Start Setting Inductor Selection Output Capacitor Selection Input Capacitor Selection Low-Side Power Device Selection Programming the UVLO Input Compensation Components Design Power Dissipation Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown Junction Temperature Design Examples Setting the Switching Frequency Setting the Output Voltage Setting the Current Limit Selecting the Inductor Selecting the Output Capacitor Selecting the Low-Side MOSFET Designing the Compensation Network Selecting the Soft Start Time Selecting the Input Capacitor Printed Circuit Board Layout Recommendations Typical Application Circuit Factory Default Options Outline Dimensions Ordering Guide