Datasheet ADP5054 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | Quad Buck Regulator Integrated Power Solution |
| Páginas / Página | 31 / 3 — Data Sheet. ADP5054. REVISION HISTORY 6/2018—Rev. D to Rev. E. … |
| Revisión | G |
| Formato / tamaño de archivo | PDF / 837 Kb |
| Idioma del documento | Inglés |
Data Sheet. ADP5054. REVISION HISTORY 6/2018—Rev. D to Rev. E. 10/2017—Rev. C to Rev. D. 9/2015—Rev. A to Rev. B
Versión de texto del documento
Data Sheet ADP5054 REVISION HISTORY 6/2018—Rev. D to Rev. E
Deleted Factory Programmable Options Section and Table 14 to Changes to Forced PWM and Automatic PWM/PSM Table 18; Renumbered Sequential y.. 29 Modes Section .. 15 Changes to Factory Default Options Section .. 29 Change to Figure 44 .. 29 Added Endnote 1, Table 14 .. 29
10/2017—Rev. C to Rev. D 9/2015—Rev. A to Rev. B
Changes to Figure 1... 1 Changes to Figure 1 and Table 1 ... 1 Changes to Precision Enabling Section .. 15 Changes to Figure 2 .. 3 Changes to Figure 44 .. 29 Changes to Table 3 .. 5 Updated Outline Dimensions .. 30 Changes to Figure 44 .. 28 Changes to Ordering Guide ... 30
4/2015—Rev. 0 to Rev. A 11/2016—Rev. B to Rev. C
Changes to Figure 3 .. 8 Changes to Figure 1... 1 Changes to Figure 29 .. 15
3/2015—Revision 0: Initial Version
Rev. E | Page 3 of 31 Document Outline Features Applications Typical Application Circuit General Description Revision History Detailed Functional Block Diagram Specifications Buck Regulator Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Buck Regulator Operational Modes PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes Adjustable and Fixed Output Voltage Internal Regulators (VREG and VDD) Separate Supply Applications Low-Side Device Selection Bootstrap Circuitry Active Output Discharge Switch Precision Enabling Oscillator Phase Shift Synchronization Input/Output Soft Start Parallel Operation Startup with Precharged Output Current-Limit Protection Frequency Foldback Pulse Skip in Maximum Duty Short-Circuit Protection (SCP) Latch-Off Protection Short-Circuit Latch-Off Mode Undervoltage Lockout (UVLO) Power-Good Function Thermal Shutdown Applications Information ADIsimPower Design Tool Programming the Output Voltage Voltage Conversion Limitations Current-Limit Setting Soft Start Setting Inductor Selection Output Capacitor Selection Input Capacitor Selection Low-Side Power Device Selection Programming the UVLO Input Compensation Components Design Power Dissipation Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown Junction Temperature Design Examples Setting the Switching Frequency Setting the Output Voltage Setting the Current Limit Selecting the Inductor Selecting the Output Capacitor Selecting the Low-Side MOSFET Designing the Compensation Network Selecting the Soft Start Time Selecting the Input Capacitor Printed Circuit Board Layout Recommendations Typical Application Circuit Factory Default Options Outline Dimensions Ordering Guide
Deleted Factory Programmable Options Section and Table 14 to Changes to Forced PWM and Automatic PWM/PSM Table 18; Renumbered Sequential y.. 29 Modes Section .. 15 Changes to Factory Default Options Section .. 29 Change to Figure 44 .. 29 Added Endnote 1, Table 14 .. 29
10/2017—Rev. C to Rev. D 9/2015—Rev. A to Rev. B
Changes to Figure 1... 1 Changes to Figure 1 and Table 1 ... 1 Changes to Precision Enabling Section .. 15 Changes to Figure 2 .. 3 Changes to Figure 44 .. 29 Changes to Table 3 .. 5 Updated Outline Dimensions .. 30 Changes to Figure 44 .. 28 Changes to Ordering Guide ... 30
4/2015—Rev. 0 to Rev. A 11/2016—Rev. B to Rev. C
Changes to Figure 3 .. 8 Changes to Figure 1... 1 Changes to Figure 29 .. 15
3/2015—Revision 0: Initial Version
Rev. E | Page 3 of 31 Document Outline Features Applications Typical Application Circuit General Description Revision History Detailed Functional Block Diagram Specifications Buck Regulator Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Buck Regulator Operational Modes PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes Adjustable and Fixed Output Voltage Internal Regulators (VREG and VDD) Separate Supply Applications Low-Side Device Selection Bootstrap Circuitry Active Output Discharge Switch Precision Enabling Oscillator Phase Shift Synchronization Input/Output Soft Start Parallel Operation Startup with Precharged Output Current-Limit Protection Frequency Foldback Pulse Skip in Maximum Duty Short-Circuit Protection (SCP) Latch-Off Protection Short-Circuit Latch-Off Mode Undervoltage Lockout (UVLO) Power-Good Function Thermal Shutdown Applications Information ADIsimPower Design Tool Programming the Output Voltage Voltage Conversion Limitations Current-Limit Setting Soft Start Setting Inductor Selection Output Capacitor Selection Input Capacitor Selection Low-Side Power Device Selection Programming the UVLO Input Compensation Components Design Power Dissipation Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown Junction Temperature Design Examples Setting the Switching Frequency Setting the Output Voltage Setting the Current Limit Selecting the Inductor Selecting the Output Capacitor Selecting the Low-Side MOSFET Designing the Compensation Network Selecting the Soft Start Time Selecting the Input Capacitor Printed Circuit Board Layout Recommendations Typical Application Circuit Factory Default Options Outline Dimensions Ordering Guide