Datasheet ATmega163, ATmega163L - Summary (Atmel) - 3

ATmega163(L) Description
The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architec- ture. By executing powerful instructions in a single clock cycle, the ATmega163 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram Figure 1.
Block Diagram PA0 - PA7 PC0 - PC7 VCC PORTA DRIVERS PORTC DRIVERS GND DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTA REG. PORTA PORTC REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX ADC OSCILLATOR AGND 2-WIRE SERIAL XTAL1 AREF INTERFACE INTERNAL INTERNAL REFERENCE OSCILLATOR OSCILLATOR XTAL2 PROGRAM STACK WATCHDOG TIMING AND RESET COUNTER POINTER TIMER CONTROL PROGRAM MCU CONTROL SRAM FLASH REGISTER INSTRUCTION GENERAL TIMER/ REGISTER PURPOSE COUNTERS REGISTERS X INSTRUCTION INTERRUPT Y DECODER UNIT Z CONTROL ALU EEPROM LINES INTERNAL STATUS CALIBRATED REGISTER OSCILLATOR PROGRAMMING SPI LOGIC UART TOR DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. + - PORTB REG. PORTB PORTD REG. PORTD ARA ANALOG COMP PORTB DRIVERS PORTD DRIVERS PB0 - PB7 PD0 - PD7 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock
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1142ES–AVR–02/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 Erratas ATmega163(L) Errata Rev. F ChangeLog Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03