Datasheet AD8450 (Analog Devices) - 5

AD8450 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Small Signal −3 dB Bandwidth Gain = 26 1.5 MHz Gain = 66 630 kHz Gain = 133 330 kHz Gain = 200 220 kHz Slew Rate ΔVISMEA = 10 V 5 V/µs VOLTAGE SENSE PGDA Internal Fixed Gains 0.2, 0.27, 0.4, 0.8 V/V Gain Error VIN = ±10 V ±0.1 % Gain Drift TA = TMIN to TMAX 3 ppm/°C Gain Nonlinearity VBVMEA = ±10 V, RL = 2 kΩ 3 ppm Offset Voltage (RTO) BVREFH and BVREFL pins grounded 500 µV Offset Voltage Drift TA = TMIN to TMAX 4 µV/°C Differential Input Voltage Range Gain = 0.8, VBVN0 = 0 V, VBVREFL = 0 V AVCC = +15 V, AVEE = −15 V −16 +16 V AVCC = +25 V, AVEE = −5 V −4 +29 V Input Common-Mode Voltage Range Gain = 0.8, VBVMEA = 0 V AVCC = +15 V, AVEE = −15 V −27 +27 V AVCC = +25 V, AVEE = −5 V −7 +50 V Differential Input Impedance Gain = 0.2 800 kΩ Gain = 0.27 600 kΩ Gain = 0.4 400 kΩ Gain = 0.8 200 kΩ Input Common-Mode Impedance Gain = 0.2 240 kΩ Gain = 0.27 190 kΩ Gain = 0.4 140 kΩ Gain = 0.8 90 kΩ Output Voltage Swing AVEE + 1.5 AVCC − 1.5 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1.7 V Capacitive Load Drive 1000 pF Short-Circuit Current 30 mA Reference Input Voltage Range BVREFH and BVREFL pins tied together AVEE AVCC V Output Voltage Level Shift BVREFL pin grounded Maximum BVREFH pin connected to VREF pin 4.5 5 5.5 mV Scale Factor VBVMEA/VBVREFH 1.8 2 2.2 mV/V CMRR ΔVCM = 10 V, all fixed gains, RTO 80 dB Temperature Coefficient TA = TMIN to TMAX 0.05 µV/V/°C PSRR ΔVS = 20 V, all fixed gains, RTO 100 dB Output Voltage Noise f = 1 kHz, RTI Gain = 0.2 325 nV/√Hz Gain = 0.27 250 nV/√Hz Gain = 0.4 180 nV/√Hz Gain = 0.8 105 nV/√Hz Voltage Noise, Peak-to-Peak f = 0.1 Hz to 10 Hz, RTI Gain = 0.2 6 µV p-p Gain = 0.27 5 µV p-p Gain = 0.4 3 µV p-p Gain = 0.8 2 µV p-p Rev. B | Page 4 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PGIA CHARACTERISTICS PGDA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER VINT BUFFER CURRENT SHARING AMPLIFIER COMPARATORS REFERENCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Gain Selection Reversing Polarity When Charging and Discharging PGIA Offset Option Battery Reversal and Overvoltage Protection PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA) CC AND CV LOOP FILTER AMPLIFIERS COMPENSATION VINT BUFFER MODE PIN, CHARGE AND DISCHARGE CONTROL OVERCURRENT AND OVERVOLTAGE COMPARATORS CURRENT SHARING BUS AND IMAX OUTPUT APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS POWER SUPPLY SEQUENCING POWER-ON SEQUENCE POWER-OFF SEQUENCE PGIA CONNECTIONS Current Sensors Optional Low-Pass Filter PGDA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) OVERVOLTAGE AND OVERCURRENT COMPARATORS STEP BY STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices ADDITIONAL INFORMATION EVALUATION BOARD INTRODUCTION FEATURES AND TESTS TESTING THE AD8450-EVALZ PGIA and Offset PGIA Gain Test PGIA in an Application Simple Offset Test Offset in an Application PGDA and Offset Simple Test PGDA in an Application PGDA Offset Overload Comparators VSET Buffer CV and CC Loop Filter Amplifiers CC and CV Integrator Tests Uncommitted Op Amp USING THE AD8450 SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE