Data SheetAD8450SPECIFICATIONS AVCC = +25 V, AVEE = −5 V; AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; PGIA gain = 26, 66, 133, or 200; PGDA gain = 0.2, 0.27, 0.4, or 0.8; TA = 25°C, unless otherwise noted. Table 1. ParameterTest Conditions/CommentsMinTypMaxUnit CURRENT SENSE PGIA Internal Fixed Gains 26, 66, 133, 200 V/V Gain Error VISMEA = ±10 V ±0.1 % Gain Drift TA = TMIN to TMAX 3 ppm/°C Gain Nonlinearity VISMEA = ±10 V, RL = 2 kΩ 3 ppm Offset Voltage (RTI) Gain = 200, ISREFH and ISREFL pins −110 +110 µV grounded Offset Voltage Drift TA = TMIN to TMAX 0.6 µV/°C Input Bias Current 15 30 nA Temperature Coefficient TA = TMIN to TMAX 150 pA/°C Input Offset Current 2 nA Temperature Coefficient TA = TMIN to TMAX 10 pA/°C Input Common-Mode Voltage Range VISVP − VISVN = 0 V AVEE + 2.3 AVCC − 2.4 V Over Temperature TA = TMIN to TMAX AVEE + 2.6 AVCC − 2.6 V Overvoltage Input Range AVCC − 55 AVEE + 55 V Differential Input Impedance 150 GΩ Input Common-Mode Impedance 150 GΩ Output Voltage Swing AVEE + 1.5 AVCC − 1.2 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1.4 V Capacitive Load Drive 1000 pF Short-Circuit Current 40 mA Reference Input Voltage Range ISREFH and ISREFL pins tied together AVEE AVCC V Reference Input Bias Current VISVP = VISVN = 0 V 5 µA Output Voltage Level Shift ISREFL pin grounded Maximum ISREFH pin connected to VREF pin 17 20 23 mV Scale Factor VISMEA/VISREFH 6.8 8 9.2 mV/V CMRR ΔVCM = 20 V Gain = 26 108 dB Gain = 66 116 dB Gain = 133 122 dB Gain = 200 126 dB Temperature Coefficient TA = TMIN to TMAX 0.01 µV/V/°C PSRR ΔVS = 20 V Gain = 26 108 122 dB Gain = 66 116 130 dB Gain = 133 122 136 dB Gain = 200 126 140 dB Voltage Noise f = 1 kHz Gain = 26 9 nV/√Hz Gain = 66 8 nV/√Hz Gain = 133 7 nV/√Hz Gain = 200 7 nV/√Hz Voltage Noise, Peak-to-Peak f = 0.1 Hz to 10 Hz, all fixed gains 0.2 µV p-p Current Noise f = 1 kHz 80 fA/√Hz Current Noise, Peak-to-Peak f = 0.1 Hz to 10 Hz 5 pA p-p Rev. B | Page 3 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PGIA CHARACTERISTICS PGDA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER VINT BUFFER CURRENT SHARING AMPLIFIER COMPARATORS REFERENCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Gain Selection Reversing Polarity When Charging and Discharging PGIA Offset Option Battery Reversal and Overvoltage Protection PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA) CC AND CV LOOP FILTER AMPLIFIERS COMPENSATION VINT BUFFER MODE PIN, CHARGE AND DISCHARGE CONTROL OVERCURRENT AND OVERVOLTAGE COMPARATORS CURRENT SHARING BUS AND IMAX OUTPUT APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS POWER SUPPLY SEQUENCING POWER-ON SEQUENCE POWER-OFF SEQUENCE PGIA CONNECTIONS Current Sensors Optional Low-Pass Filter PGDA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) OVERVOLTAGE AND OVERCURRENT COMPARATORS STEP BY STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices ADDITIONAL INFORMATION EVALUATION BOARD INTRODUCTION FEATURES AND TESTS TESTING THE AD8450-EVALZ PGIA and Offset PGIA Gain Test PGIA in an Application Simple Offset Test Offset in an Application PGDA and Offset Simple Test PGDA in an Application PGDA Offset Overload Comparators VSET Buffer CV and CC Loop Filter Amplifiers CC and CV Integrator Tests Uncommitted Op Amp USING THE AD8450 SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE