Datasheet AD8450 (Analog Devices)
Fabricante | Analog Devices |
Descripción | Precision Analog Front End and Controller for Battery Test/Formation Systems |
Páginas / Página | 42 / 1 — Precision Analog Front End and Control er. for Battery Test/Formation … |
Revisión | B |
Formato / tamaño de archivo | PDF / 1.4 Mb |
Idioma del documento | Inglés |
Precision Analog Front End and Control er. for Battery Test/Formation Systems. Data Sheet. AD8450. FEATURES. GENERAL DESCRIPTION
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Precision Analog Front End and Control er for Battery Test/Formation Systems Data Sheet AD8450 FEATURES GENERAL DESCRIPTION Integrated constant current and voltage modes with
The AD8450 is a precision analog front end and control er for
automatic switchover
testing and monitoring battery cells. A precision programmable
Charge and discharge modes
gain instrumentation amplifier (PGIA) measures the battery
Precision voltage and current measurement
charge/discharge current, and a programmable gain difference
Integrated precision control feedback blocks
amplifier (PGDA) measures the battery voltage (see Figure 1).
Precision interface to PWM or linear power converters
Internal laser trimmed resistor networks set the gains for the
Programmable gain settings
PGIA and the PGDA, optimizing the performance of the
Current sense gains: 26, 66, 133, and 200
AD8450 over the rated temperature range. PGIA gains are 26,
Voltage sense gains: 0.2, 0.27, 0.4, and 0.8
66, 133, and 200. PGDA gains are 0.2, 0.27, 0.4, and 0.8.
Programmable OVP and OCP fault detection
Voltages at the ISET and VSET inputs set the desired constant
Current sharing and balancing
current (CC) and constant voltage (CV) values. CC to CV
Excellent ac and dc performance
switching is automatic and transparent to the system.
Maximum offset voltage drift: 0.6 µV/°C Maximum gain drift: 3 ppm/°C
A TTL logic level input, MODE, selects the charge or discharge
Low current sense amplifier input voltage noise: ≤9 nV/√Hz
mode (high for charge, low for discharge). An analog output,
Current sense CMRR: 126 dB minimum (gain = 200)
VCTRL, interfaces directly with the Analog Devices, Inc.,
TTL compliant logic
ADP1972 PWM controller.
APPLICATIONS
The AD8450 includes resistor programmable overvoltage and overcurrent detection and current sharing circuitry. Current
Battery cell formation and testing
sharing is used to balance the output current of multiple
Battery module testing
bridged channels. The AD8450 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with functionality, and overall reliability in a space-saving package. The AD8450 is available in an 80-lead, 14 mm × 14 mm × 1 mm LQFP package and is rated for an operating temperature of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM ISREFH/ IVE0/ ISREFL ISMEA ISET IVE1 VINT AD8450 ISVP CSH CONSTANT CURRENT GAIN CURRENT LOOP SHARING 26, 66, IMAX NETWORK FILTER 133, 200 AND MUX VCLP ISVN CURRENT SENSE PGIA 1× VCTRL (CHARGE/ MODE DISCHARGE) SWITCHING VCLN VOLTAGE SENSE PGDA BVPx VOLTAGE VREF REFERENCE GAIN 0.2, 0.27, CONSTANT NETWORK 0.4, 0.8 VOLTAGE LOOP BVNx FILTER FAULT FAULT DETECTION
001
BVREFH/ BVMEA VSET VVE0/ VVP0 VSETBF VINT OVPS/ OCPS/ BVREFL VVE1 OVPR OCPR
1966- 1 Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PGIA CHARACTERISTICS PGDA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER VINT BUFFER CURRENT SHARING AMPLIFIER COMPARATORS REFERENCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Gain Selection Reversing Polarity When Charging and Discharging PGIA Offset Option Battery Reversal and Overvoltage Protection PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA) CC AND CV LOOP FILTER AMPLIFIERS COMPENSATION VINT BUFFER MODE PIN, CHARGE AND DISCHARGE CONTROL OVERCURRENT AND OVERVOLTAGE COMPARATORS CURRENT SHARING BUS AND IMAX OUTPUT APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS POWER SUPPLY SEQUENCING POWER-ON SEQUENCE POWER-OFF SEQUENCE PGIA CONNECTIONS Current Sensors Optional Low-Pass Filter PGDA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) OVERVOLTAGE AND OVERCURRENT COMPARATORS STEP BY STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices ADDITIONAL INFORMATION EVALUATION BOARD INTRODUCTION FEATURES AND TESTS TESTING THE AD8450-EVALZ PGIA and Offset PGIA Gain Test PGIA in an Application Simple Offset Test Offset in an Application PGDA and Offset Simple Test PGDA in an Application PGDA Offset Overload Comparators VSET Buffer CV and CC Loop Filter Amplifiers CC and CV Integrator Tests Uncommitted Op Amp USING THE AD8450 SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE