Datasheet LTC4313-1, LTC4313-2, LTC4313-3 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 2-Wire Bus Buffers with High Noise Margin |
| Páginas / Página | 20 / 8 — applicaTions inForMaTion. Rise Time Accelerator (RTA) Pull-Up Current … |
| Formato / tamaño de archivo | PDF / 296 Kb |
| Idioma del documento | Inglés |
applicaTions inForMaTion. Rise Time Accelerator (RTA) Pull-Up Current Strength. (LTC4313-1 and LTC4313-2)
Línea de modelo para esta hoja de datos
- LTC4313CDD-1#PBF LTC4313CDD-1#TRPBF LTC4313CDD-2#PBF LTC4313CDD-2#TRPBF LTC4313CDD-3#PBF LTC4313CDD-3#TRPBF LTC4313CMS8-1#PBF LTC4313CMS8-1#TRPBF LTC4313CMS8-2#PBF LTC4313CMS8-2#TRPBF LTC4313CMS8-3#PBF LTC4313CMS8-3#TRPBF LTC4313IDD-1#PBF LTC4313IDD-1#TRPBF LTC4313IDD-2#PBF LTC4313IDD-2#TRPBF LTC4313IDD-3#PBF LTC4313IDD-3#TRPBF LTC4313IMS8-1#PBF LTC4313IMS8-1#TRPBF LTC4313IMS8-2#PBF LTC4313IMS8-2#TRPBF LTC4313IMS8-3#PBF LTC4313IMS8-3#TRPBF
- LTC4313CDD-1#PBF LTC4313CDD-1#TRPBF LTC4313CMS8-1#PBF LTC4313CMS8-1#TRPBF LTC4313IDD-1#PBF LTC4313IDD-1#TRPBF LTC4313IMS8-1#PBF LTC4313IMS8-1#TRPBF
Versión de texto del documento
LTC4313-1/LTC4313-2/ LTC4313-3
applicaTions inForMaTion
The LTC4313 provides capacitance buffering, data and of 75V/µs. The current is therefore directly proportional clock Hot Swap capability and level translation. The high to the bus capacitance. The LTC4313-1 RTA is capable of noise margin of the LTC4313 permits interoperability with sourcing up to 40mA of current. Rise time acceleration I2C devices that drive a high VOL permits series connec- for the LTC4313-2 is provided by a 2.5mA current source. tion of multiple LTC4313s and improves I2C communica- Figures 1 and 2 show the rising waveforms of heavily tion reliability. The LTC4313 isolates backplane and card loaded SDAIN and SDAOUT busses for the LTC4313-1 and capacitances and provides slew control of falling edges LTC4313-2 respectively. In both figures, during a rising while level translating 3.3V and 5V busses. The LTC4313-1 edge, the buffers are active and the input and output sides and LTC4313-2 also provide pull-up currents to accelerate are connected, until the bus voltages on both the input rising edges. These features are illustrated in the following and output sides are greater than 0.3 • V subsections. CC. When each individual bus voltage rises above 0.41 • VCC, the RTA on
Rise Time Accelerator (RTA) Pull-Up Current Strength
that bus turns on. The effect of the acceleration strength
(LTC4313-1 and LTC4313-2)
is shown in the waveforms in Figures 1 and 2 for identi- cal bus loads. The RTAs of the LTC4313-1 and LTC4313-2 After an input and output connection has been established, supply 10mA and 2.5mA of pul -up current respectively for the RTAs on both the input and output sides of the SDA the bus conditions shown in Figures 1 and 2. For identical and SCL busses are activated. During positive bus transi- bus loads, the bus rises faster in Figure 1 compared to tions of at least 0.4V/µs, the RTAs provide pull-up cur- Figure 2 because of the higher IRTA. rents to reduce rise time. The RTAs allow users to choose larger bus pull-up resistors to reduce power consumption The RTAs are internally disabled during power-up and dur- and improve logic low noise margins, design with bus ing a bus stuck low event. The RTAs when activated pull capacitances outside of the I2C specification or to oper- the bus up to 0.9•VCC on the input and output sides of the ate at a higher clock frequency. The LTC4313-1 regulates SDA and SCL pins. In order to prevent bus overdrive by its RTA current to limit the bus rise rate to a maximum the RTA, the bus supplies on the input and output sides SDAOUT SDAOUT SDAIN SDAIN 2V/DIV VCC = VDD,BUS = 5V 2V/DIV VCC = VDD,BUS = 5V RBUS = 20k RBUS = 20k CIN = COUT = 200pF CIN = COUT = 200pF 1µs/DIV 4313123 F01 1µs/DIV 4313123 F02
Figure 1. Bus Rising Edge for the LTC4313-1. VCC = VDD,BUS = 5V Figure 2. Bus Rising Edge for the LTC4313-2. VCC = VDD,BUS = 5V
4313123f 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts
applicaTions inForMaTion
The LTC4313 provides capacitance buffering, data and of 75V/µs. The current is therefore directly proportional clock Hot Swap capability and level translation. The high to the bus capacitance. The LTC4313-1 RTA is capable of noise margin of the LTC4313 permits interoperability with sourcing up to 40mA of current. Rise time acceleration I2C devices that drive a high VOL permits series connec- for the LTC4313-2 is provided by a 2.5mA current source. tion of multiple LTC4313s and improves I2C communica- Figures 1 and 2 show the rising waveforms of heavily tion reliability. The LTC4313 isolates backplane and card loaded SDAIN and SDAOUT busses for the LTC4313-1 and capacitances and provides slew control of falling edges LTC4313-2 respectively. In both figures, during a rising while level translating 3.3V and 5V busses. The LTC4313-1 edge, the buffers are active and the input and output sides and LTC4313-2 also provide pull-up currents to accelerate are connected, until the bus voltages on both the input rising edges. These features are illustrated in the following and output sides are greater than 0.3 • V subsections. CC. When each individual bus voltage rises above 0.41 • VCC, the RTA on
Rise Time Accelerator (RTA) Pull-Up Current Strength
that bus turns on. The effect of the acceleration strength
(LTC4313-1 and LTC4313-2)
is shown in the waveforms in Figures 1 and 2 for identi- cal bus loads. The RTAs of the LTC4313-1 and LTC4313-2 After an input and output connection has been established, supply 10mA and 2.5mA of pul -up current respectively for the RTAs on both the input and output sides of the SDA the bus conditions shown in Figures 1 and 2. For identical and SCL busses are activated. During positive bus transi- bus loads, the bus rises faster in Figure 1 compared to tions of at least 0.4V/µs, the RTAs provide pull-up cur- Figure 2 because of the higher IRTA. rents to reduce rise time. The RTAs allow users to choose larger bus pull-up resistors to reduce power consumption The RTAs are internally disabled during power-up and dur- and improve logic low noise margins, design with bus ing a bus stuck low event. The RTAs when activated pull capacitances outside of the I2C specification or to oper- the bus up to 0.9•VCC on the input and output sides of the ate at a higher clock frequency. The LTC4313-1 regulates SDA and SCL pins. In order to prevent bus overdrive by its RTA current to limit the bus rise rate to a maximum the RTA, the bus supplies on the input and output sides SDAOUT SDAOUT SDAIN SDAIN 2V/DIV VCC = VDD,BUS = 5V 2V/DIV VCC = VDD,BUS = 5V RBUS = 20k RBUS = 20k CIN = COUT = 200pF CIN = COUT = 200pF 1µs/DIV 4313123 F01 1µs/DIV 4313123 F02
Figure 1. Bus Rising Edge for the LTC4313-1. VCC = VDD,BUS = 5V Figure 2. Bus Rising Edge for the LTC4313-2. VCC = VDD,BUS = 5V
4313123f 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts