Datasheet LTC4312 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers |
| Páginas / Página | 20 / 3 — ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply … |
| Formato / tamaño de archivo | PDF / 200 Kb |
| Idioma del documento | Inglés |
ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating
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LTC4312
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply/Start-Up
VCC Input Supply Range l 2.9 5.5 V VDD, BUS 2-Wire Bus Supply Voltage l 2.25 5.5 V VCC2 Output Side Accelerator Supply l 2.25 5.5 V Range ICC Input Supply Current One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l 6.0 7.3 9 mA ICC(DISABLED) Input Supply Current VENABLE1-2 = 0V; VCC = VCC2 = 5.5V (Note 3) l 1.6 2.2 3.5 mA ICC2 VCC2 Supply Current One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l 0.35 0.5 0.6 mA tUVLO UVLO Delay l 60 110 200 μs VTH_UVLO UVLO Threshold l 2.3 2.6 V VCC_UVLO(HYST) UVLO Threshold Hysteresis 200 mV Voltage
Buffers
VOS1(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAIN,SCLIN = 50mV l 130 220 280 mV IOL = 500μA, Driven VSDAIN,SCLIN = 50mV l 15 60 120 mV VOS2(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT,SCLOUT = 50mV l 90 190 260 mV IOL = 500μA, Driven VSDAOUT,SCLOUT = 50mV l 15 55 110 mV VOS Buffer Offset Voltage IOL = 4mA, Driven VSDAIN,SCLIN = 200mV l 50 130 195 mV IOL = 500μA, Driven VSDAIN,SCLIN = 200mV l 15 55 110 mV VOS2 Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT,SCLOUT = 200mV l 35 95 170 mV IOL = 500μA, Driven VSDAOUT,SCLOUT = 200mV l 15 50 100 mV VIL,FALLING Buffer Input Logic Low Voltage SDA, SCL Pins (Notes 4, 5) l 0.3•VMIN 0.33•VMIN 0.36•VMIN V VIL,RISING Buffer Input Logic Low Voltage SDA, SCL Pins; ACC Grounded l 0.5 0.6 0.7 V SDA, SCL Pins; ACC Open or High (Notes 4, 5) l 0.3•VMIN 0.33•VMIN 0.36•VMIN V ILEAK Input Leakage Current SDA, SCL Pins; VCC, VCC2 = 0V, 5.5V l ±10 μA CIN Input Capacitance SDA, SCL Pins (Note 6) <20 pF
Rise Time Accelerators
dV/dt (RTA) Minimum Slew Rate Requirement SDA, SCL Pins; VCC = VCC2 = 5V l 0.1 0.2 0.4 V/μs VRTA(TH) Rise Time Accelerator DC SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 0.7 0.8 0.9 V Threshold Voltage ACC Open or High, VCC = VCC2 = 5V (Note 4) l 0.36•VMIN 0.4•VMIN 0.44•VMIN V ΔVACC Buffers Off to Accelerator On SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 100 200 mV Voltage ACC Open, VCC = VCC2 = 5V (Note 4) l 0.05•VMIN 0.07•VMIN mV IRTA Rise Time Accelerator Pull-Up SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 20 35 45 mA Current (Note 7) ACC Open, VCC = VCC2 = 5V (Note 7) l 1.5 3 4 mA
Enable/Control
VDISCEN(TH) DISCEN Threshold Voltage l 0.8 1.4 2 V ΔVDISCEN(HYST) DISCEN Hysteresis Voltage 20 mV VEN(TH) ENABLE1-2 Threshold Voltage l 0.8 1.4 2 V ΔVEN(HYST) ENABLE1-2 Hysteresis Voltage 20 mV tLH_EN ENABLE1-2 High to Buffer Active 0.56 1 μs 4312f 3
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply/Start-Up
VCC Input Supply Range l 2.9 5.5 V VDD, BUS 2-Wire Bus Supply Voltage l 2.25 5.5 V VCC2 Output Side Accelerator Supply l 2.25 5.5 V Range ICC Input Supply Current One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l 6.0 7.3 9 mA ICC(DISABLED) Input Supply Current VENABLE1-2 = 0V; VCC = VCC2 = 5.5V (Note 3) l 1.6 2.2 3.5 mA ICC2 VCC2 Supply Current One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l 0.35 0.5 0.6 mA tUVLO UVLO Delay l 60 110 200 μs VTH_UVLO UVLO Threshold l 2.3 2.6 V VCC_UVLO(HYST) UVLO Threshold Hysteresis 200 mV Voltage
Buffers
VOS1(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAIN,SCLIN = 50mV l 130 220 280 mV IOL = 500μA, Driven VSDAIN,SCLIN = 50mV l 15 60 120 mV VOS2(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT,SCLOUT = 50mV l 90 190 260 mV IOL = 500μA, Driven VSDAOUT,SCLOUT = 50mV l 15 55 110 mV VOS Buffer Offset Voltage IOL = 4mA, Driven VSDAIN,SCLIN = 200mV l 50 130 195 mV IOL = 500μA, Driven VSDAIN,SCLIN = 200mV l 15 55 110 mV VOS2 Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT,SCLOUT = 200mV l 35 95 170 mV IOL = 500μA, Driven VSDAOUT,SCLOUT = 200mV l 15 50 100 mV VIL,FALLING Buffer Input Logic Low Voltage SDA, SCL Pins (Notes 4, 5) l 0.3•VMIN 0.33•VMIN 0.36•VMIN V VIL,RISING Buffer Input Logic Low Voltage SDA, SCL Pins; ACC Grounded l 0.5 0.6 0.7 V SDA, SCL Pins; ACC Open or High (Notes 4, 5) l 0.3•VMIN 0.33•VMIN 0.36•VMIN V ILEAK Input Leakage Current SDA, SCL Pins; VCC, VCC2 = 0V, 5.5V l ±10 μA CIN Input Capacitance SDA, SCL Pins (Note 6) <20 pF
Rise Time Accelerators
dV/dt (RTA) Minimum Slew Rate Requirement SDA, SCL Pins; VCC = VCC2 = 5V l 0.1 0.2 0.4 V/μs VRTA(TH) Rise Time Accelerator DC SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 0.7 0.8 0.9 V Threshold Voltage ACC Open or High, VCC = VCC2 = 5V (Note 4) l 0.36•VMIN 0.4•VMIN 0.44•VMIN V ΔVACC Buffers Off to Accelerator On SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 100 200 mV Voltage ACC Open, VCC = VCC2 = 5V (Note 4) l 0.05•VMIN 0.07•VMIN mV IRTA Rise Time Accelerator Pull-Up SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l 20 35 45 mA Current (Note 7) ACC Open, VCC = VCC2 = 5V (Note 7) l 1.5 3 4 mA
Enable/Control
VDISCEN(TH) DISCEN Threshold Voltage l 0.8 1.4 2 V ΔVDISCEN(HYST) DISCEN Hysteresis Voltage 20 mV VEN(TH) ENABLE1-2 Threshold Voltage l 0.8 1.4 2 V ΔVEN(HYST) ENABLE1-2 Hysteresis Voltage 20 mV tLH_EN ENABLE1-2 High to Buffer Active 0.56 1 μs 4312f 3