Datasheet LTC4312 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers |
| Páginas / Página | 20 / 10 — APPLICATIONS INFORMATION. Supply Voltage Considerations in Level … |
| Formato / tamaño de archivo | PDF / 200 Kb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION. Supply Voltage Considerations in Level Translation. Applications
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC4312
APPLICATIONS INFORMATION
If VCC2 is tied low, the output side rise time accelerators
Supply Voltage Considerations in Level Translation
are disabled independent of the state of the ACC pin.
Applications
ACC tied high disables input and output RTAs. Using a Care must be taken to ensure that the bus supply voltages combination of the ACC pin and the VCC2 voltage allows on the input and output sides are greater than 0.9•V the user independent control of the input and output side CC and 0.8•V rise time accelerators. The rise time accelerators are also CC2, respectively, to ensure that the bus is not driven above the bus supplies by the rise time accelerators. This internally disabled during power-up and VCC2 transitions, is usually accomplished in a level shifting application by as described in the Operation section, as well as during tying V automatic clocking and stop bit generation for a bus stuck CC to the input bus supply and VCC2 to the minimum bus supply on the output side as shown in Figure 3. low recovery event. If V The rise time accelerators when activated pull the bus up CC2 is grounded, the multiplexer pass gates are powered from V to 0.9•V CC. In this case the minimum output bus supply CC on the input side of the SDA and SCL lines. of the enabled channels should be greater than or equal On the output side the SDAOUT and SCLOUT lines are to V pulled up by the rise time accelerators to 0.8•V CC to prevent cross-conduction between the enabled CC2. For output channels. This is shown in Figure 4. Grounding V V CC2 CC2 voltages approaching 2.3V, acceleration of the output as shown in Figure 4 disables the output side rise time bus may not be seen all the way to 0.8•VCC2 due to the accelerators independent of the state of the ACC pin. The threshold voltage of the NFET pass device. input rise time accelerators in this confi guration continue to be controlled by the ACC pin and can be enabled inde- pendently. In Figure 4, ACC is left open to obtain a high VIL and a 3mA rise time accelerator current on the input side. 3.3V 3.3V C1 C2 R1 R2 0.01μF V R4 R5 CC VCC2 0.01μF 10k 10k 10k 10k SCLIN SCLIN SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 LTC4312 5V 3.3V R6 R7 R3 ACC 10k 10k 10k SCLOUT2 SCLOUT2 DISCEN SDAOUT2 SDAOUT2 FAULT FAULT GND 4312 F03
Figure 3. Connection of the LTC4312 in a Level Shift Application. VCC2 Is Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side
4312f 10
APPLICATIONS INFORMATION
If VCC2 is tied low, the output side rise time accelerators
Supply Voltage Considerations in Level Translation
are disabled independent of the state of the ACC pin.
Applications
ACC tied high disables input and output RTAs. Using a Care must be taken to ensure that the bus supply voltages combination of the ACC pin and the VCC2 voltage allows on the input and output sides are greater than 0.9•V the user independent control of the input and output side CC and 0.8•V rise time accelerators. The rise time accelerators are also CC2, respectively, to ensure that the bus is not driven above the bus supplies by the rise time accelerators. This internally disabled during power-up and VCC2 transitions, is usually accomplished in a level shifting application by as described in the Operation section, as well as during tying V automatic clocking and stop bit generation for a bus stuck CC to the input bus supply and VCC2 to the minimum bus supply on the output side as shown in Figure 3. low recovery event. If V The rise time accelerators when activated pull the bus up CC2 is grounded, the multiplexer pass gates are powered from V to 0.9•V CC. In this case the minimum output bus supply CC on the input side of the SDA and SCL lines. of the enabled channels should be greater than or equal On the output side the SDAOUT and SCLOUT lines are to V pulled up by the rise time accelerators to 0.8•V CC to prevent cross-conduction between the enabled CC2. For output channels. This is shown in Figure 4. Grounding V V CC2 CC2 voltages approaching 2.3V, acceleration of the output as shown in Figure 4 disables the output side rise time bus may not be seen all the way to 0.8•VCC2 due to the accelerators independent of the state of the ACC pin. The threshold voltage of the NFET pass device. input rise time accelerators in this confi guration continue to be controlled by the ACC pin and can be enabled inde- pendently. In Figure 4, ACC is left open to obtain a high VIL and a 3mA rise time accelerator current on the input side. 3.3V 3.3V C1 C2 R1 R2 0.01μF V R4 R5 CC VCC2 0.01μF 10k 10k 10k 10k SCLIN SCLIN SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 LTC4312 5V 3.3V R6 R7 R3 ACC 10k 10k 10k SCLOUT2 SCLOUT2 DISCEN SDAOUT2 SDAOUT2 FAULT FAULT GND 4312 F03
Figure 3. Connection of the LTC4312 in a Level Shift Application. VCC2 Is Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side
4312f 10