Datasheet AD5686, AD5684 (Analog Devices) - 11
| Fabricante | Analog Devices |
| Descripción | Quad, 16-/12-Bit nanoDAC+ with SPI Interface |
| Páginas / Página | 27 / 11 — Data Sheet. AD5686/AD5684. TYPICAL PERFORMANCE CHARACTERISTICS. 1.0. 0.8. … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 757 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD5686/AD5684. TYPICAL PERFORMANCE CHARACTERISTICS. 1.0. 0.8. 0.6. 0.4. 0.2. B) S. L ( IN. DNL –0.2. –0.4. –0.6. VDD = 5V. DD = 5V. –0.8
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Data Sheet AD5686/AD5684 TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 8 0.8 6 0.6 4 0.4 ) 2 0.2 B B) S LS L 0 ( 0 L ( IN –2 DNL –0.2 –4 –0.4 –6 –0.6 V VDD = 5V –8 DD = 5V –0.8 T T A = 25°C A = 25°C REFERENCE = 2.5V REFERENCE = 2.5V –10 –1.0
18
0 10000 20000 30000 40000 50000 60000
1
0 625 1250 1875 2500 3125 3750 4096
123
CODE CODE
10797- 10797- Figure 8. AD5686 INL Figure 11. AD5684 DNL
10 10 8 8 6 6 4 4 B) ) 2 2 S INL B L LS 0 R ( 0 L ( DNL IN –2 RRO –2 E –4 –4 –6 –6 V –8 DD = 5V –8 VDD = 5V TA = 25°C REFERENCE = 2.5V REFERENCE = 2.5V –10 –10
124
0 625 1250 1875 2500 3125 3750 4096
120
–40 10 60 110 TEMPERATURE (°C) CODE
10797- 10797- Figure 9. AD5684 INL Figure 12. INL Error and DNL Error vs. Temperature
10 1.0 8 0.8 6 0.6 4 0.4 B) 2 0.2 S INL B) L S L R ( 0 ( 0 DNL RRO DNL –2 –0.2 E –4 –0.4 V –6 DD = 5V –0.6 TA = 25°C V –8 –0.8 DD = 5V TA = 25°C REFERENCE = 2.5V –10 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
125
0 10000 20000 30000 40000 50000 60000
121
V CODE REF (V)
10797- 10797- Figure 10. AD5686 DNL Figure 13. INL Error and DNL Error vs. VREF Rev. C | Page 11 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE
18
0 10000 20000 30000 40000 50000 60000
1
0 625 1250 1875 2500 3125 3750 4096
123
CODE CODE
10797- 10797- Figure 8. AD5686 INL Figure 11. AD5684 DNL
10 10 8 8 6 6 4 4 B) ) 2 2 S INL B L LS 0 R ( 0 L ( DNL IN –2 RRO –2 E –4 –4 –6 –6 V –8 DD = 5V –8 VDD = 5V TA = 25°C REFERENCE = 2.5V REFERENCE = 2.5V –10 –10
124
0 625 1250 1875 2500 3125 3750 4096
120
–40 10 60 110 TEMPERATURE (°C) CODE
10797- 10797- Figure 9. AD5684 INL Figure 12. INL Error and DNL Error vs. Temperature
10 1.0 8 0.8 6 0.6 4 0.4 B) 2 0.2 S INL B) L S L R ( 0 ( 0 DNL RRO DNL –2 –0.2 E –4 –0.4 V –6 DD = 5V –0.6 TA = 25°C V –8 –0.8 DD = 5V TA = 25°C REFERENCE = 2.5V –10 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
125
0 10000 20000 30000 40000 50000 60000
121
V CODE REF (V)
10797- 10797- Figure 10. AD5686 DNL Figure 13. INL Error and DNL Error vs. VREF Rev. C | Page 11 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE