Datasheet AD5686, AD5684 (Analog Devices) - 3

link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 13 link to page 13 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
Data Sheet AD5686/AD5684 SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2 AD5686 Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 LSB Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5684 Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of All 1s loaded to DAC register FSR Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of Gain = 2 FSR ±0.25 ±0.2 % of Gain = 1 FSR Offset Error Drift3 ±1 ±1 µV/°C Gain Temperature ±1 ±1 ppm Of FSR/°C Coefficient3 DC Power Supply Rejection 0.15 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% Ratio3 DC Crosstalk3 ±2 ±2 µV Due to single channel, full-scale output change ±3 ±3 µV/mA Due to load current change ±2 ±2 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VREF 0 VREF V Gain = 1 0 2 × VREF 0 2 × VREF V Gain = 2, see Figure 23 Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 1 kΩ Resistive Load4 1 1 kΩ Load Regulation 80 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA 80 80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA Short-Circuit Current5 40 40 mA Load Impedance at Rails6 25 25 Ω See Figure 23 Power-Up Time 2.5 2.5 µs Coming out of power-down mode; VDD = 5 V REFERENCE INPUT Reference Current 90 90 µA VREF = VDD = VLOGIC = 5.5 V, gain = 1 180 180 µA VREF = VDD = VLOGIC = 5.5 V, gain = 2 Reference Input Range 1 VDD 1 VDD V Gain = 1 1 VDD/2 1 VDD/2 V Gain = 2 Reference Input Impedance 16 16 kΩ Gain = 2 32 32 kΩ Gain = 1 Rev. C | Page 3 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE