Datasheet AD5686, AD5684 (Analog Devices)

Quad, 16-/12-Bit nano DAC+ with SPI Interface Data Sheet AD5686/ AD5684 FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum @ 16 bits V GND V DD REF Tiny package: 3 mm × 3 mm, 16-lead LFCSP AD5686/AD5684 Total unadjusted error (TUE): ±0.1% of FSR maximum VLOGIC Offset error: ±1.5 mV maximum INPUT DAC STRING V REGISTER REGISTER DAC A OUTA Gain error: ±0.1% of FSR maximum SCLK BUFFER High drive capability: 20 mA, 0.5 V from supply rails INPUT DAC STRING VOUTB SYNC REGISTER REGISTER DAC B User selectable gain of 1 or 2 (GAIN pin) LOGIC E BUFFER C Reset to zero scale or midscale (RSTSEL pin) FA SDIN R INPUT DAC STRING V REGISTER REGISTER DAC C OUTC 1.8 V logic compatibility TE IN BUFFER 50 MHz SPI with readback or daisy chain SDO INPUT DAC STRING VOUTD Low glitch: 0.5 nV-sec REGISTER REGISTER DAC D BUFFER Low power: 1.8 mW at 3 V POWER-ON GAIN POWER- RESET ×1/×2 DOWN 2.7 V to 5.5 V power supply LOGIC
001
−40°C to +105°C temperature range LDAC RESET RSTSEL GAIN
10797-
APPLICATIONS
Figure 1.
Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION
The AD5686/AD5684, members of the nanoDAC+™ family, are
Table 1. Quad nano DAC+ Devices
low power, quad, 16-/12-bit buffered voltage output DACs.
Interface Reference 16-Bit 14-Bit 12-Bit
The devices include a gain select pin giving a full-scale output SPI Internal AD5686R AD5685R AD5684R of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from SPI External AD5686 AD5684 a single 2.7 V to 5.5 V supply, are guaranteed monotonic by I2C Internal AD5696R AD5695R AD5694R design, and exhibit less than 0.1% FSR gain error and 1.5 mV I2C External AD5696 AD5694 offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.
PRODUCT HIGHLIGHTS
The AD5686/AD5684 also incorporate a power-on reset circuit 1. High Relative Accuracy (INL). and a RSTSEL pin that ensures that the DAC outputs power up AD5686 (16-bit): ±2 LSB maximum to zero scale or midscale and remain at that level until a valid AD5684 (12-bit): ±1 LSB maximum write takes place. Each part contains a per-channel power-down 2. Excel ent DC Performance. feature that reduces the current consumption of the device to Total unadjusted error: ±0.1% of FSR maximum 4 µA at 3 V while in power-down mode. Offset error: ±1.5 mV maximum The AD5686/AD5684 employ a versatile SPI interface that Gain error: ±0.1% of FSR maximum operates at clock rates up to 50 MHz, and all devices contain 3. Two Package Options. a VLOGIC pin intended for 1.8 V/3 V/5 V logic. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE