Datasheet AD7716 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | CMOS, 4-Channel, 22-Bit Data Acquisition System |
| Páginas / Página | 17 / 5 — AD7716. MASTER MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V. 5%; … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 473 Kb |
| Idioma del documento | Inglés |
AD7716. MASTER MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V. 5%; AVSS= –5 V
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AD7716 MASTER MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V
6
5%; AVSS= –5 V
6
5%; AGND = DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments
f 3, 4 CLKIN 400 kHz min CLKIN Frequency 8 MHz max t 5 r 40 ns max Digital Output Rise Time. Typically 20 ns t 5 f 40 ns max Digital Output Fall Time. Typically 20 ns t7 1/fCLKIN ns min CASCIN Pulse Width t8 1/fCLKIN ns min CASCIN to DRDY Setup Time t9 1/2fCLKIN + 30 ns max DRDY Low to SCLK Low Delay t10 50 ns max CLKIN High to DRDY Low, SCLK Active, RFS Active t11 40 ns max CLKIN High to SCLK High Delay t12 50 ns min SCLK Width t13 1/fCLKIN ns SCLK Period t14 40 ns max SCLK High to RFS High Delay t15 1/fCLKIN ns RFS Pulse Width t 6 16 45 ns max SCLK High to SDATA Valid Delay t 7 17 1/2fCLKIN + 50 ns max SCLK Low to SDATA High Impedance Delay 1/2fCLKIN + 10 ns min t18 1/2fCLKIN + 60 ns max CLKIN High to DRDY High Delay t19 50 ns max CLKIN High to RFS High Impedance, SCLK High Impedance 20 ns min t20 1/2fCLKIN + 50 ns max SCLK Low to CASCOUT High Delay t21 2/fCLKIN ns CASCOUT Pulse Width NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 1 and 3. 3CLKIN duty cycle range is 40% to 60%. 4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode. 5Specified using 10% and 90% points on waveform of interest. 6t16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 7t17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
t7 CASCIN (I) t8 CLKIN (I) t t 9 18 t11 DRDY (O) t t t t 10 12 13 19 SCLK (O) t t t t 12 14 15 19 RFS (O) t t17 16 DB31 DB30 DB29 DB25 DB24 DB23 DB2 DB1 DB0 SDATA (O) CH1 CH1 CH1 CH1 CH1 CH1 CH4 CH4 CH4 t21 t20 CASCOUT (O)
Figure 3. Master Mode Timing Diagram –4– REV. A
6
5%; AVSS= –5 V
6
5%; AGND = DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments
f 3, 4 CLKIN 400 kHz min CLKIN Frequency 8 MHz max t 5 r 40 ns max Digital Output Rise Time. Typically 20 ns t 5 f 40 ns max Digital Output Fall Time. Typically 20 ns t7 1/fCLKIN ns min CASCIN Pulse Width t8 1/fCLKIN ns min CASCIN to DRDY Setup Time t9 1/2fCLKIN + 30 ns max DRDY Low to SCLK Low Delay t10 50 ns max CLKIN High to DRDY Low, SCLK Active, RFS Active t11 40 ns max CLKIN High to SCLK High Delay t12 50 ns min SCLK Width t13 1/fCLKIN ns SCLK Period t14 40 ns max SCLK High to RFS High Delay t15 1/fCLKIN ns RFS Pulse Width t 6 16 45 ns max SCLK High to SDATA Valid Delay t 7 17 1/2fCLKIN + 50 ns max SCLK Low to SDATA High Impedance Delay 1/2fCLKIN + 10 ns min t18 1/2fCLKIN + 60 ns max CLKIN High to DRDY High Delay t19 50 ns max CLKIN High to RFS High Impedance, SCLK High Impedance 20 ns min t20 1/2fCLKIN + 50 ns max SCLK Low to CASCOUT High Delay t21 2/fCLKIN ns CASCOUT Pulse Width NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 1 and 3. 3CLKIN duty cycle range is 40% to 60%. 4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode. 5Specified using 10% and 90% points on waveform of interest. 6t16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 7t17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
t7 CASCIN (I) t8 CLKIN (I) t t 9 18 t11 DRDY (O) t t t t 10 12 13 19 SCLK (O) t t t t 12 14 15 19 RFS (O) t t17 16 DB31 DB30 DB29 DB25 DB24 DB23 DB2 DB1 DB0 SDATA (O) CH1 CH1 CH1 CH1 CH1 CH1 CH4 CH4 CH4 t21 t20 CASCOUT (O)
Figure 3. Master Mode Timing Diagram –4– REV. A