Datasheet AD7716 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | CMOS, 4-Channel, 22-Bit Data Acquisition System |
| Páginas / Página | 17 / 6 — AD7716. SLAVE MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V. 5%; … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 473 Kb |
| Idioma del documento | Inglés |
AD7716. SLAVE MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V. 5%; AVSS = –5 V
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AD7716 SLAVE MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V
6
5%; AVSS = –5 V
6
5%; AGND = DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted) Parameter (B Version) Units Conditions/Comments
f 3, 4 CLKIN 400 kHz min CLKIN Frequency 8 MHz max t 5 r 40 ns max Digital Output Rise Time. Typically 20 ns t 5 f 40 ns max Digital Output Fall Time. Typically 20 ns t23 1/fCLKIN ns min CASCIN Pulse Width t24 50 ns min SCLK Width t25 125 ns min SCLK Period t26 1/fCLKIN +30 ns min CASCIN High to RFS Setup Time t27 30 ns min RFS Low to SCLK High Setup Time t 6 28 50 ns max SCLK High to SDATA Valid Delay t29 50 ns min RFS Hold Time After SCLK High t 7 30 50 ns max SCLK High to SDATA High Impedance Delay 0 ns min t31 60 ns max SCLK High to CASCOUT High Delay. t32 2/fCLKIN ns max CASCOUT Pulse Width NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 1 and 4. 3CLKIN duty cycle range is 40% to 60%. 4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz. 5Specified using 10% and 90% points on waveform of interest. 6t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 7t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
t23 CASCIN (I) t t 24 25 SCLK (I) t t 26 24 t t 29 27 RFS (I) t t 28 30 SDATA (O) DB31 DB30 DB29 DB28 DB27 DB2 DB1 DB0 CH1 CH1 CH1 CH1 CH1 CH4 CH4 CH4 t t 31 32 CASCOUT (O)
Figure 4. Slave Mode Timing Diagram REV. A –5–
6
5%; AVSS = –5 V
6
5%; AGND = DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted) Parameter (B Version) Units Conditions/Comments
f 3, 4 CLKIN 400 kHz min CLKIN Frequency 8 MHz max t 5 r 40 ns max Digital Output Rise Time. Typically 20 ns t 5 f 40 ns max Digital Output Fall Time. Typically 20 ns t23 1/fCLKIN ns min CASCIN Pulse Width t24 50 ns min SCLK Width t25 125 ns min SCLK Period t26 1/fCLKIN +30 ns min CASCIN High to RFS Setup Time t27 30 ns min RFS Low to SCLK High Setup Time t 6 28 50 ns max SCLK High to SDATA Valid Delay t29 50 ns min RFS Hold Time After SCLK High t 7 30 50 ns max SCLK High to SDATA High Impedance Delay 0 ns min t31 60 ns max SCLK High to CASCOUT High Delay. t32 2/fCLKIN ns max CASCOUT Pulse Width NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 1 and 4. 3CLKIN duty cycle range is 40% to 60%. 4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz. 5Specified using 10% and 90% points on waveform of interest. 6t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 7t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
t23 CASCIN (I) t t 24 25 SCLK (I) t t 26 24 t t 29 27 RFS (I) t t 28 30 SDATA (O) DB31 DB30 DB29 DB28 DB27 DB2 DB1 DB0 CH1 CH1 CH1 CH1 CH1 CH4 CH4 CH4 t t 31 32 CASCOUT (O)
Figure 4. Slave Mode Timing Diagram REV. A –5–