Datasheet AD7851 (Analog Devices) - 5

AD7851 Parameter Version A1 Version K1 Unit Test Conditions/Comments
POWER PERFORMANCE AVDD, DVDD 4.75/5.25 4.75/5.25 V min/max IDD Normal Mode4 17 17 mA max AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA. Sleep Mode5 With External Clock On 20 20 µA typ Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 600 600 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 300 300 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 89.25 89.25 mW max VDD = 5.25 V: Typically 63 mW; SLEEP = VDD. Sleep Mode Power Dissipation With External Clock On 105 105 µW typ VDD = 5.25 V; SLEEP = 0 V. With External Clock Off 52.5 52.5 µW max VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V. SYSTEM CALIBRATION Offset Calibration Span6 +0.05 × VREF/–0.05 × VREF V max/min Allowable Offset Voltage Span for Calibration. Gain Calibration Span6 +1.025 × VREF/–0.975 × VREF V max/min Allowable Full-Scale Voltage Span for Calibration. NOTES 1Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C. 2Specifications apply after calibration. 3SNR calculation includes distortion and noise components. 4All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND. 5CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND. 6The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF). This is explained in more detail in the Calibration section of the data sheet. Specifications subject to change without notice. –4– REV. B Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS SPECIFICATIONS TIMING SPECIFICATIONS TYPICAL TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS PINOUT FOR DIP, SOIC, AND SSOP ORDERING GUIDE TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error Unipolar Offset Error Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Power Supply Rejection Ratio (PSRR) Full Power Bandwidth (FPBW) PIN FUNCTION DESCRIPTIONS AD7851 ON-CHIP REGISTERS Addressing the On-Chip Registers Writing Reading CONTROL REGISTER STATUS REGISTER CALIBRATION REGISTERS Addressing the Calibration Registers Writing to/Reading from the Calibration Registers Adjusting the Offset Calibration Register Adjusting the Gain Calibration Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUT Acquisition Time DC/AC Applications Input Ranges Transfer Functions REFERENCE SECTION AD7851 PERFORMANCE CURVES POWER-DOWN OPTIONS POWER-UP TIMES Using an External Reference Using the Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE CALIBRATION SECTION Calibration Overview Automatic Calibration on Power-On Self-Calibration Description Self-Calibration Timing System Calibration Description System Gain and Offset Interaction System Calibration Timing SERIAL INTERFACE SUMMARY Resetting the Serial Interface DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) MODE 4 and 5 (Self-Clocking Modes) CONFIGURING THE AD7851 AD7851 as a Read-Only ADC Writing to the AD7851 Interface Modes 2 and 3 Configuration Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration MICROPROCESSOR INTERFACING AD7851 to 8XC51/PIC17C42 Interface AD7851 to 68HC11/16/L11/PIC16C42 Interface AD7851 to ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface AD7851 to TMS320C20/25/5x/LC5x Interface APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance AD785x Family OUTLINE DIMENSIONS Revision History