Datasheet AD7851 (Analog Devices) - 6

AD7851 TIMING SPECIFICATIONS1 (AVDD = DVDD = 5.0 V
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5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted.)
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin LOW, then the opposite edge of SCLK will apply.
Limit at TMIN, TMAX Parameter (A, K Versions) Unit Description
f 2 CLKIN 500 kHz min Master Clock Frequency 7 MHz max f 3 SCLK 10 MHz max Interface Modes 1, 2, 3 (External Serial Clock) fCLK IN MHz max Interface Modes 4, 5 (Internal Serial Clock) t 4 1 100 ns min CONVST Pulse Width t2 50 ns max CONVST↓ to BUSY↑ Propagation Delay tCONVERT 3.25 µs max Conversion Time = 20 tCLKIN t3 –0.4 tSCLK ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input) ±0.4 tSCLK ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input) t4 0.6 tSCLK ns min SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only t 5 5 30 ns max Delay from SYNC↓ until DOUT Three-State Disabled t 5 5A 30 ns max Delay from SYNC↓ until DIN Three-State Disabled t 5 6 45 ns max Data Access Time after SCLK↓ t7 30 ns min Data Setup Time prior to SCLK↑ t8 20 ns min Data Valid to SCLK Hold Time t 6 9 0.4 tSCLK ns min SCLK High Pulse Width (Interface Modes 4 and 5) t 6 10 0.4 tSCLK ns min SCLK Low Pulse Width (Interface Modes 4 and 5) t11 30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 30/0.4 tSCLK ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 t11A 50 ns max SCLK↑ to SYNC↑ Hold Time t 7 12 50 ns max Delay from SYNC↑ until DOUT Three-State Enabled t13 90 ns max Delay from SCLK↑ to DIN Being Configured as Output t 8 14 50 ns max Delay from SCLK↑ to DIN Being Configured as Input t15 2.5 tCLKIN ns max CAL↑ to BUSY↑ Delay t16 2.5 tCLKIN ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence t 9 CAL 41.7 ms typ Full Self-Calibration Time, Master Clock Dependent (250026 tCLKIN) t 9 CAL1 37.04 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master Clock Dependent (222228 tCLKIN) t 9 CAL2 4.63 ms typ System Offset Calibration Time, Master Clock Dependent (27798 tCLKIN) tDELAY 65 ns max Delay from CLK to SCLK NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Table X and timing diagrams for different interface modes and calibration. 2Mark/space ratio for the master clock input is 40/60 to 60/40. 3For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f CLKIN. 4The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power- Down section). 5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN. 7The time t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t 12 as quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 8 The time t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing that a bus conflict will not occur. 9The typical time specified for the calibration times is for a master clock of 6 MHz. Specifications subject to change without notice. REV. B –5– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS SPECIFICATIONS TIMING SPECIFICATIONS TYPICAL TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS PINOUT FOR DIP, SOIC, AND SSOP ORDERING GUIDE TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error Unipolar Offset Error Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Power Supply Rejection Ratio (PSRR) Full Power Bandwidth (FPBW) PIN FUNCTION DESCRIPTIONS AD7851 ON-CHIP REGISTERS Addressing the On-Chip Registers Writing Reading CONTROL REGISTER STATUS REGISTER CALIBRATION REGISTERS Addressing the Calibration Registers Writing to/Reading from the Calibration Registers Adjusting the Offset Calibration Register Adjusting the Gain Calibration Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUT Acquisition Time DC/AC Applications Input Ranges Transfer Functions REFERENCE SECTION AD7851 PERFORMANCE CURVES POWER-DOWN OPTIONS POWER-UP TIMES Using an External Reference Using the Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE CALIBRATION SECTION Calibration Overview Automatic Calibration on Power-On Self-Calibration Description Self-Calibration Timing System Calibration Description System Gain and Offset Interaction System Calibration Timing SERIAL INTERFACE SUMMARY Resetting the Serial Interface DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) MODE 4 and 5 (Self-Clocking Modes) CONFIGURING THE AD7851 AD7851 as a Read-Only ADC Writing to the AD7851 Interface Modes 2 and 3 Configuration Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration MICROPROCESSOR INTERFACING AD7851 to 8XC51/PIC17C42 Interface AD7851 to 68HC11/16/L11/PIC16C42 Interface AD7851 to ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface AD7851 to TMS320C20/25/5x/LC5x Interface APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance AD785x Family OUTLINE DIMENSIONS Revision History