Datasheet AD7895 (Analog Devices) - 9

AD7895
than the 9.8 µs shown in diagram from the rising edge of valid on the first falling edge of SCLK even though the data CONVST. This is because the Track/Hold amplifier goes into access time is specified at 60 ns for the other bits. The reason its hold mode on the falling edge of CONVST, and the conver- that the first bit will be clocked out faster than the other bits is sion will not be complete for a further 3.8 µs. In this case, the due to the internal architecture of the part. Sixteen clock pulses BUSY will be the best indicator for when the conversion is must be provided to the part to access to full conversion result. complete. Even though the part is in sleep mode, data can still The AD7895 provides four leading zeros, followed by the 12-bit be read from the part. The read operation consists of 16 clock conversion result starting with the MSB (DB11). The last data cycles as in Mode 1 Operation. For the fastest serial clock of bit to be clocked out on the penultimate falling clock edge is the 15 MHz, the read operation will take 1.1 µs and this must be LSB (DB0). On the sixteenth falling edge of SCLK, the LSB complete at least 300 ns before the falling edge of the next (DB0) will be valid for a specified time to allow the bit to be CONVST to allow the Track/Hold amplifier to have enough read on the falling edge of the SCLK, then the SDATA line is time to settle. This mode is very useful when the part is convert- disabled (three-stated). After this last bit has been clocked ing at a slow rate as the power consumption will be significantly out, the SCLK input should return low and remain low until the reduced from that of Mode 1 Operation. next serial data read operation. If there are extra clock pulses
Serial Interface
after the sixteenth clock, the AD7895 will start over again with The serial interface to the AD7895 consists of just three wires: a outputting data from its output register, and the data bus will no serial clock input (SCLK), the serial data output (SDATA) and longer be three-stated even when the clock stops. Provided the a conversion status output (BUSY). This allows for an easy-to- serial clock has stopped before the next falling edge of CONVST, use interface to most microcontrollers, DSP processors and shift the AD7895 will continue to operate correctly with the output registers. shift register being reset on the falling edge of CONVST. However, the SCLK line must be low when CONVST goes low in Figure 5 shows the timing diagram for the read operation to the order to reset the output shift register correctly. AD7895. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked out from the The serial clock input does not have to be continuous during the SDATA line on the falling edge of this clock and is valid on serial read operation. The sixteen bits of data (four leading both the rising and falling edges of SCLK. The advantage of zeros and 12 bit conversion result) can be read from the AD7895 having the data valid on both the rising and falling edges of the in a number of bytes. SCLK is that it gives the user greater flexibility in interfacing to The AD7895 counts the serial clock edges to know which bit the part and allows a wider range of microprocessor and micro- from the output register should be placed on the SDATA controller interfaces to be accommodated. This also explains the output. To ensure that the part does not lose synchronization, two timing figures, t4 and t5, that are quoted on the diagram. the serial clock counter is reset on the falling edge of the The time t4 specifies how long after the falling edge of the CONVST input, provided the SCLK line is low. The user SCLK that the next data bit becomes valid, whereas the time t5 should ensure that the SCLK line remains low until the end of specifies how long after the falling edge of the SCLK that the the conversion. When the conversion is complete, BUSY goes current data bit is valid for. The first leading zero is clocked out low, the output register will be loaded with the new conversion on the first rising edge of SCLK. Note that the first zero will be result and can be read from with sixteen clock cycles of SCLK.
t1 = 6µs WAKE-UP t1 TIME CONVST BUSY 300ns MIN SCLK tCONVERT = 9.8µs PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED ENDS OPERATION SHOULD END 300ns SERIAL UP TRACK/HOLD 9.8µs LATER PRIOR TO NEXT SHIFT GOES INTO FALLING EDGE OF REGISTER HOLD CONVST IS RESET
Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
t2 = t3 = 35ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 50ns MAX @ 5V, A, B, VERSIONS t2 SCLK (I/P) 1 2 3 4 5 6 15 16 t3 t5 t6 t 3-STATE 4 4 LEADING ZEROS 3-STATE DOUT (O/P) DB11 DB10 DB0
Figure 5. Data Read Operation –8– REV. 0