Datasheet AD7895 (Analog Devices) - 10

AD7895 MICROPROCESSOR/MICROCONTROLLER INTERFACE AD7895–68HC11/L11 Interface
The AD7895 provides a three-wire serial interface that can be An interface circuit between the AD7895 and the 68HC11/L11 used for connection to the serial ports of DSP processors and microcontroller is shown in Figure 7. For the interface shown, microcontrollers. Figures 6 through 9 show the AD7895 the 68L11 SPI port is used, and the 68L11 is configured in its interfaced to a number of different microcontrollers and DSP single-chip mode. The 68L11 is configured in the master mode processors. The AD7895 accepts an external serial clock, and with its CPOL bit set to a logic zero and its CPHA bit set to a as a result, in all interfaces shown here, the processor/controller logic one. As with the previous interface, the diagram shows the is configured as the master, providing the serial clock with the simplest form of the interface where the AD7895 is the only part AD7895 configured as the slave in the system. connected to the serial port of the 68L11 and, therefore, no decoding of the serial read operations is required.
AD7895–8051 Interface
Figure 6 shows an interface between the AD7895 and the 8XL51 microcontroller. The 8XL51 is configured for its Mode 0 serial interface mode. The diagram shows the simplest form of the
PC2 OR BUSY IRQ
interface where the AD7895 is the only part connected to the
AD7895
serial port of the 8XL51 and, therefore, no decoding of the
68HC11/L11
serial read operations is required.
SCK SCLK MISO SDATA P1.2 OR BUSY INT1 AD7895 8X51/L51
Figure 7. AD7895 to 68HC11/L11 Interface
P3.0 SDATA
Once again, to chip select the AD7895 in systems where more than one device is connected to the 68HC11’s serial port, a port
P3.1 SCLK
bit configured as an output from one of the 68HC11’s parallel ports can be used to gate on or off the serial clock to the AD7895. A simple AND function on this port bit and the serial Figure 6. AD7895 to 8X51/L51 Interface clock from the 68L11 will provide this function. The port bit To chip select the AD7895 in systems where more than one should be high to select the AD7895 and low when it is not device is connected to the 8XL51’s serial port, a port bit selected. configured as an output, from one of the 8XL51’s parallel ports The end of conversion is monitored by using the BUSY signal can be used to gate on or off the serial clock to the AD7895. A that is shown in the interface diagram of Figure 7. With the simple AND function on this port bit and the serial clock from BUSY line from the AD7895 connected to the Port PC0 of the the 8XL51 will provide this function. The port bit should be 68HC11/L11, the BUSY line can be polled by the 68HC11/L11. high to select the AD7895 and low when it is not selected. The BUSY line can be connected to the IRQ line of the The end of conversion is monitored by using the BUSY signal 68HC11/L11 if an interrupt driven system is preferred. These that is shown in the interface diagram of Figure 6. The BUSY two options are shown in the diagram. line from the AD7895 is connected to the Port P1.2 of the The serial clock rate from the 68HC11/L11 is limited to 8XL51 so the BUSY line can be polled by the 8XL51. The BUSY significantly less than the allowable input serial clock frequency line can be connected to the INT1 line of the 8XL51 if an with which the AD7895 can operate. As a result, the time to interrupt driven system is preferred. These two options are read data from the part will actually be longer than the conver- shown in the diagram. sion time of the part. This means that the AD7895 cannot run Note also that the AD7895 outputs the MSB first during a read at its maximum throughput rate when used with the 68HC11/L11. operation, while the 8XL51 expects the LSB first. Therefore,
AD7895–ADSP-2103/5 Interface
the data which is read into the serial buffer needs to be rear- An interface circuit between the AD7895 and the ADSP-2103/5 ranged before the correct data format from the AD7895 appears DSP processor is shown in Figure 8. In the interface shown, the in the accumulator. RFS1 output from the ADSP-2103/5s SPORT1 serial port is The serial clock rate from the 8XL51 is limited to significantly used to gate the serial clock (SCLK1) of the ADSP-2103/5 less than the allowable input serial clock frequency with which before it is applied to the SCLK input of the AD7895. The the AD7895 can operate. As a result, the time to read data RFS1 output is configured for active high operation. The BUSY from the part will actually be longer than the conversion time of line from the AD7895 is connected to the IRQ2 line of the the part. This means that the AD7895 cannot run at its maximum ADSP-2103/5 so that at the end of conversion an interrupt is throughput rate when used with the 8XL51. generated telling the ADSP-2103/5 to initiate a read operation. The interface ensures a noncontinuous clock for the AD7895’s serial clock input with only sixteen serial clock pulses provided and the serial clock line of the AD7895 remaining low between data transfers. The SDATA line from the AD7895 is connected to the DR1 line of the ADSP-2103/5’s serial port. REV. 0 –9–