Datasheet AD7895 (Analog Devices) - 8

AD7895
The track/hold amplifier acquires an input signal to 12-bit stated. If there are more serial clock pulses after the sixteenth accuracy in less than 0.3 µs. The operation of the track/hold is clock, the shift register will be moved on past its reset state. essentially transparent to the user. With the high sampling However, the shift register will be reset again on the falling edge operating mode, the track/hold amplifier goes from its tracking of the CONVST signal to ensure that the part returns to a mode to its hold mode at the start of conversion (i.e. the falling known state every conversion cycle. As a result, a read opera- edge of CONVST). The aperture time for the track/hold (i.e. tion from the output register should not straddle across the the delay time between the external CONVST signal and the falling edge of CONVST as the output shift register will be reset track/hold actually going into hold) is typically 15 ns. At the in the middle of the read operation, and the data read back into end of conversion (on the falling edge of BUSY), the part returns the microprocessor will appear invalid. to its tracking mode. The acquisition time of the track/hold amplifier begins at this point. For the auto shut down mode, the
OPERATING MODES
rising edge of CONVST wakes up the part and the track, and
Mode 1 Operation (High Sampling Performance)
hold amplifier goes from its tracking mode to its hold mode 6 µs The timing diagram in Figure 3 is for optimum performance in after the rising edge of CONVST (provided that the CONVST operating Mode 1 where the falling edge of CONVST starts high time is less than 6 µs). Once again, the part returns to its conversion and puts the Track/Hold amplifier into its hold tracking mode at the end of conversion when the BUSY signal mode. This falling edge of CONVST also causes the BUSY goes low. signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete,
Reference Input
The reference input to the AD7895 is buffered on-chip with a which is 3.8 µs max after the falling edge of CONVST, and new maximum reference input current of 1 µA. The part is specified data from this conversion is available in the output register of with a +2.5 V reference input voltage. Errors in the reference the AD7895. A read operation accesses this data. This read source will result in gain errors in the AD7895’s transfer operation consists of 16 clock cycles, and the length of this read function and will add to the specified full-scale errors on the operation will depend on the serial clock frequency. For the part. Suitable reference sources for the AD7895 include the fastest throughput rate (with a serial clock of 15 MHz, 5 V AD780 and AD680 precision +2.5 V references. operation) the read operation will take 1.1 µs. The read opera- tion must be complete at least 300 ns before the falling edge of
Timing and Control Section
the next CONVST, and this gives a total time of 5.2 µs for the Figure 3 shows the timing and control sequence required to full throughput time (equivalent to 192 kHz). This mode of obtain optimum performance from the AD7895. In the se- operation should be used for high sampling applications. quence shown, conversion is initiated on the falling edge of CONVST, and new data from this conversion is available in
Mode 2 Operation (Auto Sleep After Conversion)
the output register of the AD7895 3.8 µs later. Once the read The timing diagram in Figure 4 is for optimum performance in operation has taken place, a further 300 ns should be allowed operating mode 2 where the part automatically goes into sleep before the next falling edge of CONVST to optimize the settling mode once BUSY goes low after conversion and “wakes-up” of the track/hold amplifier before the next conversion is initi- before the next conversion takes place. This is achieved by keep- ated. With the serial clock frequency at its maximum of ing CONVST low at the end of conversion, whereas it was high 15 MHz, the achievable throughput rate for the part is 3.8 µs at the end of conversion for Mode 1 Operation. The rising edge (conversion time) plus 1.1 µs (read time) plus 0.3 µs (acquisi- of CONVST “wakes up” the part. This wake-up time is 6 µs at tion time). This results in a minimum throughput time of 8.2 µs which point the Track/Hold amplifier goes into its hold mode, (equivalent to a throughput rate of 192 kHz). A serial clock of provided the CONVST has gone low. The conversion takes less than 15 MHz can be used, but this will in turn mean that 3.8 µs after this giving a total of 9.8 µs from the rising edge of the throughput time will increase. CONVST to the conversion being complete, which is indi- cated by the BUSY going low. Note that since the wake-up time The read operation consists of sixteen serial clock pulses to the from the rising edge of CONVST is 6 µs, when the CONVST output shift register of the AD7895. After sixteen serial clock pulse width is greater than 6 µs, the conversion will take more pulses, the shift register is reset, and the SDATA line is three-
t t 1 1 = 40ns MIN CONVST BUSY 300ns MIN SCLK tCONVERT = 3.8µs CONVERSION IS CONVERSION SERIAL READ READ OPERATION OUTPUT ENDS INITIATED AND OPERATION SHOULD END 300ns SERIAL 3.8µs LATER TRACK/HOLD GOES INTO PRIOR TO NEXT SHIFT HOLD FALLING EDGE OF REGISTER CONVST IS RESET
Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance REV. 0 –7–