Datasheet AD7476A, AD7477A, AD7478A (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 8-Bit, 1 MSPS, Low-Power A/D Converter in SC70 and MSOP Packages |
| Páginas / Página | 28 / 6 — AD7476A/AD7477A/AD7478A. Data Sheet. Parameter. A Grade2. Unit. Test … |
| Revisión | G |
| Formato / tamaño de archivo | PDF / 548 Kb |
| Idioma del documento | Inglés |
AD7476A/AD7477A/AD7478A. Data Sheet. Parameter. A Grade2. Unit. Test Conditions/Comments. AD7478A. SPECIFICATIONS. Table 3. Parameter
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AD7476A/AD7477A/AD7478A Data Sheet Parameter A Grade2 Unit Test Conditions/Comments
POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 3.5 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 1.7 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 μA max Typically 50 nA Full Power-Down Mode (Dynamic) 0.6 mA typ VDD = 5 V, fSAMPLE = 100 kSPS Power Dissipation6 0.3 mA typ VDD = 3 V, fSAMPLE = 100 kSPS Normal Mode (Operational) 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 5.1 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down Mode 5 μW max VDD = 5 V 1 Temperature range is from −40°C to +85°C. 2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum. 3 See the Terminology section. 4 SC70 values guaranteed by characterization. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section.
AD7478A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 3. Parameter A Grade2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave Signal-to-Noise-and-Distortion (SINAD)3 49 dB min Total Harmonic Distortion (THD)3 −65 dB max Peak Harmonic or Spurious Noise (SFDR)3 −65 dB max Intermodulation Distortion (IMD)3 Second-Order Terms −76 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −76 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth 13.5 MHz typ At 3 dB 2 MHz typ At 0.1 dB DC ACCURACY Resolution 8 Bits Integral Nonlinearity3 ±0.3 LSB max Differential Nonlinearity3 ±0.3 LSB max Guaranteed no missed codes to eight bits Offset Error3, 4 ±0.3 LSB max Gain Error3, 4 ±0.3 LSB max Total Unadjusted Error (TUE)3, 4 ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to VDD V DC Leakage Current ±0.5 μA max Input Capacitance 20 pF typ Track-and-hold in track; 6 pF typ when in hold Rev. G | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
AD7476A/AD7477A/AD7478A Data Sheet Parameter A Grade2 Unit Test Conditions/Comments
POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 3.5 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 1.7 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 μA max Typically 50 nA Full Power-Down Mode (Dynamic) 0.6 mA typ VDD = 5 V, fSAMPLE = 100 kSPS Power Dissipation6 0.3 mA typ VDD = 3 V, fSAMPLE = 100 kSPS Normal Mode (Operational) 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 5.1 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down Mode 5 μW max VDD = 5 V 1 Temperature range is from −40°C to +85°C. 2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum. 3 See the Terminology section. 4 SC70 values guaranteed by characterization. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section.
AD7478A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 3. Parameter A Grade2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave Signal-to-Noise-and-Distortion (SINAD)3 49 dB min Total Harmonic Distortion (THD)3 −65 dB max Peak Harmonic or Spurious Noise (SFDR)3 −65 dB max Intermodulation Distortion (IMD)3 Second-Order Terms −76 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −76 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth 13.5 MHz typ At 3 dB 2 MHz typ At 0.1 dB DC ACCURACY Resolution 8 Bits Integral Nonlinearity3 ±0.3 LSB max Differential Nonlinearity3 ±0.3 LSB max Guaranteed no missed codes to eight bits Offset Error3, 4 ±0.3 LSB max Gain Error3, 4 ±0.3 LSB max Total Unadjusted Error (TUE)3, 4 ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to VDD V DC Leakage Current ±0.5 μA max Input Capacitance 20 pF typ Track-and-hold in track; 6 pF typ when in hold Rev. G | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS