Datasheet AD7476A, AD7477A, AD7478A (Analog Devices)

2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 Data Sheet AD7476A/ AD7477A/ AD7478A FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS VDD Specified for VDD of 2.35 V to 5.25 V Low power 12-/10-/8-BIT 3.6 mW at 1 MSPS with 3 V supplies SUCCESSIVE- VIN T/H 12.5 mW at 1 MSPS with 5 V supplies APPROXIMATION ADC Wide input bandwidth 71 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management SCLK No pipeline delays CONTROL SDATA LOGIC High speed serial interface CS SPI/QSPI™/MICROWIRE/DSP compatible Standby mode: 1 µA maximum AD7476A/AD7477A/AD7478A 6-lead SC70 package GND
02930-001
8-lead MSOP
Figure 1.
Qualified for automotive applications APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit 1. First 12-/10-/8-bit ADCs in a SC70 package. high speed, low power, successive-approximation analog-to- 2. High throughput with low power consumption. digital converters (ADCs), respectively. The parts operate from 3. Flexible power/serial clock speed management. The a single 2.35 V to 5.25 V power supply and feature throughput conversion rate is determined by the serial clock, allowing rates up to 1 MSPS. The parts contain a low noise, wide the conversion time to be reduced through the serial clock bandwidth track-and-hold amplifier that can handle input speed increase. This allows the average power consumption frequencies in excess of 13 MHz. The conversion process and to be reduced when a power-down mode is used while not data acquisition are controlled using CS and the serial clock, converting. The parts also feature a power-down mode to allowing the devices to interface with microprocessors or DSPs. maximize power efficiency at lower throughput rates. The input signal is sampled on the falling edge of CS, and the Current consumption is 1 µA maximum and 50 nA conversion is also initiated at this point. There are no pipeline typically when in power-down mode. delays associated with the parts. The AD7476A/AD7477A/ 4. Reference derived from the power supply. AD7478A use advanced design techniques to achieve low power 5. No pipeline delay. The parts feature a standard successive dissipation at high throughput rates. The reference for the part approximation ADC with accurate control of the sampling is taken internally from VDD to allow the widest dynamic input instant via a CS input and once-off conversion control. range to the ADC. Thus, the analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS