Datasheet AD9444 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 80 MSPS A/D Converter |
| Páginas / Página | 41 / 7 — AD9444. SWITCHING SPECIFICATIONS. Table 4. AD9444BSVZ-80. Parameter Temp. … |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
AD9444. SWITCHING SPECIFICATIONS. Table 4. AD9444BSVZ-80. Parameter Temp. Test. Level. Min Typ Max Unit. N–1. N+1. tCLKL. tCLKH. 1/fS. CLK+. CLK–
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AD9444 SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 10 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 (tCLKH) Full V 4 ns CLK Pulse Width Low1 (tCLKL) Full V 4 ns DATA OUTPUT PARAMETERS Output Propagation Delay—CMOS (tPD)2 (DX, DCO+) Full IV 3 5.25 8 ns Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+) Full VI 3 5 7.5 ns Pipeline Delay (Latency) Full V 12 Cycles Aperture Delay (tA) Full V ns Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–1 N A N+1 IN tCLKL tCLKH 1/fS CLK+ CLK– tPD N–12 N–11 N N+1 DATA OUT 12 CLOCK CYCLES DCO+ DCO–
05089-002
tCPD
Figure 2. LVDS Mode Timing Diagram Rev. 0 | Page 6 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE
AD9444 SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 10 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 (tCLKH) Full V 4 ns CLK Pulse Width Low1 (tCLKL) Full V 4 ns DATA OUTPUT PARAMETERS Output Propagation Delay—CMOS (tPD)2 (DX, DCO+) Full IV 3 5.25 8 ns Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+) Full VI 3 5 7.5 ns Pipeline Delay (Latency) Full V 12 Cycles Aperture Delay (tA) Full V ns Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–1 N A N+1 IN tCLKL tCLKH 1/fS CLK+ CLK– tPD N–12 N–11 N N+1 DATA OUT 12 CLOCK CYCLES DCO+ DCO–
05089-002
tCPD
Figure 2. LVDS Mode Timing Diagram Rev. 0 | Page 6 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE