Datasheet AD9444 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 80 MSPS A/D Converter |
| Páginas / Página | 41 / 6 — AD9444. DIGITAL SPECIFICATIONS. Table 3. AD9444BSVZ-80. Parameter Temp. … |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
AD9444. DIGITAL SPECIFICATIONS. Table 3. AD9444BSVZ-80. Parameter Temp. Test. Level. Min Typ. Max Unit
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 6 link to page 6
AD9444 DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full VI +200 µA Low Level Input Current Full VI −10 +10 µA Input Capacitance Full V 2 pF DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) VOD Differential Output Voltage2 Full VI 247 545 mV VOS Output Offset Voltage Full VI 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full IV 0.2 V Common-Mode Voltage Full VI 1.3 1.5 1.6 V Differential Input Resistance Full V 8 10 12 kΩ Differential Input Capacitance Full V 4 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. Rev. 0 | Page 5 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE
AD9444 DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full VI +200 µA Low Level Input Current Full VI −10 +10 µA Input Capacitance Full V 2 pF DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) VOD Differential Output Voltage2 Full VI 247 545 mV VOS Output Offset Voltage Full VI 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full IV 0.2 V Common-Mode Voltage Full VI 1.3 1.5 1.6 V Differential Input Resistance Full V 8 10 12 kΩ Differential Input Capacitance Full V 4 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. Rev. 0 | Page 5 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE