Datasheet AD9230 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter |
| Páginas / Página | 33 / 4 — AD9230. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9230-170. … |
| Formato / tamaño de archivo | PDF / 2.0 Mb |
| Idioma del documento | Inglés |
AD9230. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9230-170. AD9230-210. AD9230-250. Parameter. Temp
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AD9230 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. AD9230-170 AD9230-210 AD9230-250 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.2 4.3 4.5 mV Full −12 12 −12 12 −12 12 mV Gain Error 25°C 0.89 1.0 1.1 mV Full −1.5 3.5 −1.5 3.5 −1.5 3.5 % FS Differential Nonlinearity 25°C ±0.3 ±0.3 ±0.3 LSB (DNL) Full −0.5 0.5 −0.5 0.5 −0.6 0.6 LSB Integral Nonlinearity (INL) 25°C ±0.5 ±0.4 ±0.5 LSB Full −0.75 0.75 −0.75 0.75 −1.0 +1.0 LSB TEMPERATURE DRIFT Offset Error Full ±9 ±8 ±7 μV/°C Gain Error Full 0.019 0.021 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 136 145 154 164 181 194 mA I 3 DRVDD /SDR Mode4 Full 58 61 59 62 60 63 mA I 3 DRVDD /DDR Mode5 Full 39 40 41 mA Power Dissipation3 Full mW SDR Mode4 Full 349 371 383 407 434 463 mW DDR Mode5 Full 315 349 400 mW 1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9230. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
AD9230 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. AD9230-170 AD9230-210 AD9230-250 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.2 4.3 4.5 mV Full −12 12 −12 12 −12 12 mV Gain Error 25°C 0.89 1.0 1.1 mV Full −1.5 3.5 −1.5 3.5 −1.5 3.5 % FS Differential Nonlinearity 25°C ±0.3 ±0.3 ±0.3 LSB (DNL) Full −0.5 0.5 −0.5 0.5 −0.6 0.6 LSB Integral Nonlinearity (INL) 25°C ±0.5 ±0.4 ±0.5 LSB Full −0.75 0.75 −0.75 0.75 −1.0 +1.0 LSB TEMPERATURE DRIFT Offset Error Full ±9 ±8 ±7 μV/°C Gain Error Full 0.019 0.021 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 136 145 154 164 181 194 mA I 3 DRVDD /SDR Mode4 Full 58 61 59 62 60 63 mA I 3 DRVDD /DDR Mode5 Full 39 40 41 mA Power Dissipation3 Full mW SDR Mode4 Full 349 371 383 407 434 463 mW DDR Mode5 Full 315 349 400 mW 1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9230. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE