Datasheet AD9230 (Analog Devices)

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9230 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD (1.8V) SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.4 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) REFERENCE AD9230 SFDR = −79 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent linearity CML DRVDD DRGND DNL = ±0.3 LSB typical VIN+ TRACK-AND-HOLD VIN– INL = ±0.5 LSB typical ADC 12 OUTPUT 12 12-BIT STAGING D11 TO D0 LVDS at 250 MSPS (ANSI-644 levels) CORE LVDS 700 MHz full power analog bandwidth CLK+ CLOCK OR+ CLK– MANAGEMENT On-chip reference, no external decoupling required OR– Integrated input buffer and track-and-hold SERIAL PORT Low power dissipation DCO+ DCO– 434 mW @ 250 MSPS—LVDS SDR mode
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400 mW @ 250 MSPS—LVDS DDR mode RESET SCLK SDIO CSB
060
Programmable input voltage range
Figure 1. Functional Block Diagram
1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9230 is a 12-bit monolithic sampling analog-to-digital 1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS converter optimized for high performance, low power, and ease with a 70 MHz input. of use. The product operates at up to a 250 MSPS conversion 2. Low Power—Consumes only 434 mW @ 250 MSPS. rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary 3. Ease of Use—LVDS output data and output clock signal functions, including a track-and-hold (T/H) and voltage allow interface to current FPGA technology. The on-chip reference, are included on the chip to provide a complete signal reference and sample and hold provide flexibility in system conversion solution. design. Use of a single 1.8 V supply simplifies system power supply design. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital 4. Serial Port Control—Standard serial port interface supports outputs are LVDS (ANSI-644) compatible and support either various product functions, such as data formatting, disabling twos complement, offset binary format, or Gray code. A data the clock duty cycle stabilizer, power-down, gain adjust, clock output is available for proper output data timing. and output test pattern generation. Fabricated on an advanced CMOS process, the AD9230 is 5. Pin-Compatible Family—10-bit pin-compatible family available in a 56-lead LFCSP, specified over the industrial offered as AD9211. temperature range (−40°C to +85°C).
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE