Datasheet AD7682, AD7689 (Analog Devices) - 10

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AD7682/AD7689 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DD DD V NC N1I NC N0I N3 V I N2I N1I N0I 20 19 18 17 16 20 19 18 17 16 VDD 1 15 VIO VDD 1 15 VIO REF 2 14 SDO AD7682 REF 2 14 SDO AD7689 REFIN 3 TOP VIEW 13 SCK REFIN 3 TOP VIEW 13 SCK GND 4 (Not to Scale) 12 DIN GND 4 (Not to Scale) 12 DIN GND 5 11 CNV GND 5 11 CNV 6 7 8 9 6 7 8 9 10 10 M M NC N2I NC N3I N4 N5 I I N6I N7I CO CO NOTES NOTES 1. NC = NO CONNECT. 1. THE EXPOSED PAD IS NOT CONNECTED 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE
005
IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM
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SOLDERED TO THE SYSTEM GROUND PLANE.
07353-
GROUND PLANE.
07353- Figure 4. AD7682 LFCSP Pin Configuration Figure 5. AD7689 LFCSP Pin Configuration
Table 7. AD7682 L FCSP and AD7689 L FCSP Pin Function Descriptions AD7682 AD7689 LFCSP LFCSP Pin No. Mnemonic Mnemonic Type1 Description
1, 20 VDD VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a 2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.6 V. 2 REF REF AI/O Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. 3 REFIN REFIN AI/O Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description. 4, 5 GND GND P Power Supply Ground. 6 NC IN4 AI No Connection (AD7682). Analog Input Channel 4 (AD7689). 7 IN2 IN5 AI Analog Input Channel 2 (AD7682). Analog Input Channel 5 (AD7689). 8 NC IN6 AI No Connection (AD7682). Analog Input Channel 6 (AD7689). 9 IN3 IN7 AI Analog Input Channel 3 (AD7682). Analog Input Channel 7 (AD7689). 10 COM COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common- mode point of 0 V or VREF/2 V. 11 CNV CNV DI Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled. 12 DIN DIN DI Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Rev. H | Page 10 of 35 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagrams Unipolar or Bipolar Bipolar Single Supply Analog Inputs Input Structure Selectable Low-Pass Filter Input Configurations Sequencer Source Resistance Driver Amplifier Choice Voltage Reference Output/Input Internal Reference/Temperature Sensor External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Supplying the ADC from the Reference Digital Interface Reading/Writing During Conversion, Fast Hosts Reading/Writing After Conversion, Any Speed Hosts Reading/Writing Spanning Conversion, Any Speed Host Configuration Register, CFG General Timing Without a Busy Indicator General Timing with a Busy Indicator Channel Sequencer Examples Read/Write Spanning Conversion Without a Busy Indicator Read/Write Spanning Conversion with a Busy Indicator Applications Information Layout Evaluating the AD7682/AD7689 Performance Outline Dimensions Ordering Guide