Datasheet AD7682, AD7689 (Analog Devices) - 8

link to page 8 link to page 8
AD7682/AD7689 Data Sheet
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 5. Parameter
1
Symbol Min Typ Max Unit
CONVERSION TIME tCONV 3.2 µs CNV Rising Edge to Data Available ACQUISITION TIME tACQ 1.8 µs TIME BETWEEN CONVERSIONS tCYC 5 µs DATA WRITE/READ DURING CONVERSION tDATA 1.2 µs SCK Period tSCK tDSDO + 2 ns Low Time tSCKL 12 ns High Time tSCKH 12 ns Falling Edge to Data Remains Valid tHSDO 5 ns Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV tEN Pulse Width tCNVH 10 ns Low to SDO D15 MSB Valid VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns High or Last SCK Falling Edge to SDO High Impedance tDIS 50 ns Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA IOL TO SDO 1.4V CL 50pF
002
500µA IOH
07353- Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2
003
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
07353- Figure 3. Voltage Levels for Timing Rev. H | Page 8 of 35 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagrams Unipolar or Bipolar Bipolar Single Supply Analog Inputs Input Structure Selectable Low-Pass Filter Input Configurations Sequencer Source Resistance Driver Amplifier Choice Voltage Reference Output/Input Internal Reference/Temperature Sensor External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Supplying the ADC from the Reference Digital Interface Reading/Writing During Conversion, Fast Hosts Reading/Writing After Conversion, Any Speed Hosts Reading/Writing Spanning Conversion, Any Speed Host Configuration Register, CFG General Timing Without a Busy Indicator General Timing with a Busy Indicator Channel Sequencer Examples Read/Write Spanning Conversion Without a Busy Indicator Read/Write Spanning Conversion with a Busy Indicator Applications Information Layout Evaluating the AD7682/AD7689 Performance Outline Dimensions Ordering Guide