Datasheet AD9268 (Analog Devices) - 5

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AD9268 SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.2 ±0.4 ±0.2 ±0.5 ±0.4 ±0.65 % FSR Gain Error Full ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 % FSR Differential Full −1.0 +1.4 −1.0 +1.3 −1.0 +1.2 LSB Nonlinearity (DNL)1 25°C ±0.65 ±0.7 ±0.7 LSB Integral Nonlinearity Full ±4.5 ±5.1 ±5.5 LSB (INL)1 25°C ±2.0 ±3.0 ±3.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±0.4 ±0.1 ±0.4 ±0.2 ±0.45 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error Full ±5 ±12 ±5 ±12 ±5 ±12 mV (1 V Mode) Load Regulation @ Full 5 5 5 mV 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V 25°C 2.17 2.23 2.27 LSB rms ANALOG INPUT Input Span, VREF = Full 2 2 2 V p-p 1.0 V Input Capacitance2 Full 8 8 8 pF Input Common- Full 0.9 0.9 0.9 V Mode Voltage REFERENCE INPUT Full 6 6 6 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1 Full 234 240 293 300 390 400 mA IDRVDD1 (1.8 V Full 35 45 55 mA CMOS) IDRVDD1 (1.8 V Full 89 89 94 mA LVDS) Rev. A | Page 4 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE