Datasheet AD9268 (Analog Devices) - 10

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AD9268 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 4. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 8 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 4.5 4.75 5.0 3.8 4 4.2 ns Divide-by-2 Mode Through Divide- Full 0.8 0.8 0.8 ns by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 0.07 ps rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (tPD) Full 2.8 3.5 4.2 2.8 3.5 4.2 2.8 3.5 4.2 ns DCO Propagation Delay (tDCO)2 Full 3.1 3.1 3.1 ns DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay (tPD) Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns DCO Propagation Delay (tDCO)2 Full 3.9 3.9 3.9 ns DCO to Data Skew (tSKEW) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns CMOS Mode Pipeline Delay Full 12 12 12 Cycles (Latency) LVDS Mode Pipeline Delay (Latency) Full 12/12.5 12/12.5 12/12.5 Cycles Channel A/Channel B Wake-Up Time3 Full 500 500 500 μs Out-of-Range Recovery Time Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. A | Page 9 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE