Datasheet AD9268 (Analog Devices)

16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9268 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 78.2 dBFS @ 70 MHz and 125 MSPS SDIO/ SCLK/ AVDD CSB DRVDD DCS DFS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS SPI AD9268 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply PROGRAMMING DATA ORA Integer 1-to-8 input clock divider VIN+A D15A (MSB) CMOS/LVDS 16 ADC TO IF sampling frequencies to 300 MHz OUTPUT BUFFER VIN–A D0A (LSB) −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS DIVIDE 1 CLK+ VREF TO 8 Optional on-chip dither CLK– SENSE Programmable internal ADC voltage reference DUTY CYCLE DCO DCOA REF STABILIZER GENERATION Integrated ADC sample-and-hold inputs DCOB VCM SELECT Flexible analog input range: 1 V p-p to 2 V p-p RBIAS ORB Differential analog inputs with 650 MHz bandwidth D15B (MSB) VIN–B CMOS/LVDS 16 ADC clock duty cycle stabilizer ADC TO OUTPUT BUFFER VIN+B D0B (LSB) 95 dB channel isolation/crosstalk MULTICHIP Serial port control SYNC User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes AGND SYNC PDWN OEB NOTES
001
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; APPLICATIONS SEE FIGURE 7 FOR LVDS PIN NAMES.
08123-
Communications
Figure 1.
Diversity radio systems PRODUCT HIGHLIGHTS Multimode digital receivers (3G)
1. On-chip dither option for improved SFDR performance
GSM, EDGE, W-CDMA, LTE,
with low power analog input.
CDMA2000, WiMAX, TD-SCDMA
2. Proprietary differential input that maintains excellent SNR
I/Q demodulation systems
performance for input frequencies up to 300 MHz.
Smart antenna systems
3. Operation from a single 1.8 V supply and a separate digital
General-purpose software radios
output driver supply accommodating 1.8 V CMOS or
Broadband data applications
LVDS outputs.
Ultrasound equipment
4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 5. Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE