Datasheet AD9467 (Analog Devices) - 8

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AD9467 Data Sheet DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 3. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 0.8 0.8 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 2.5 2.5 pF LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 μA) Full 1.7/3.1 1.7/3.1 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 0.3 V DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 545 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply. Rev. D | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide