Datasheet AD9613 (Analog Devices) - 3

REFERENCE MATERIALS DESIGN RESOURCES Product Selection Guide
• AD9613 Material Declaration • RF Source Booklet • PCN-PDN Information
Technical Articles
• Quality And Reliability • MS-1779: Nine Often Overlooked ADC Specifications • Symbols and Footprints • MS-2210: Designing Power Supplies for High Speed ADC
Tutorials DISCUSSIONS
• MT-001: Taking the Mystery out of the Infamous Formula, View all AD9613 EngineerZone Discussions. "SNR=6.02N + 1.76dB", and Why You Should Care • MT-002: What the Nyquist Criterion Means to Your
SAMPLE AND BUY
Sampled Data System Design Visit the product page to see pricing options. • MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND"
TECHNICAL SUPPORT
• MT-075: Differential Drivers for High Speed ADCs Submit a technical question or find your regional support Overview number.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE