Datasheet AD9613 (Analog Devices)

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9613 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS AVDD AGND DRVDD SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and VIN+A PIPELINE 12 D0± 12-BIT . 250 MSPS VIN–A ADC . . Total power consumption: 770 mW at 250 MSPS VCM AD9613 PARALLEL . DDR LVDS . 1.8 V supply voltages VIN+B PIPELINE 12 AND D11± DRIVERS LVDS (ANSI-644 levels) outputs 12-BIT VIN–B ADC Integer 1-to-8 input clock divider (625 MHz maximum input) DCO± Sample rates of up to 250 MSPS REFERENCE IF sampling frequencies of up to 400 MHz OR± Internal ADC voltage reference 1 TO 8 SERIAL PORT CLOCK OEB Flexible analog input range DIVIDER 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) PDWN ADC clock duty cycle stabilizer SCLK SDIO CSB CLK+ CLK– SYNC 95 dB channel isolation/crosstalk NOTES
001
Serial port control 1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A AND CHANNE L B LVDS OUTPUT DATA.
09637-
Energy-saving power-down modes
Figure 1.
APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION
The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9613 is designed Programming for setup and control is accomplished using a to support communications applications where low cost, small 3-wire SPI-compatible serial interface. size, wide bandwidth, and versatility are desired. The AD9613 is available in a 64-lead LFCSP and is specified The dual ADC cores feature a multistage, differential pipelined over the industrial temperature range of −40°C to +85°C. This architecture with integrated output error correction logic. Each product is protected by a U.S. patent. ADC features wide bandwidth inputs supporting a variety of user-
PRODUCT HIGHLIGHTS
selectable input ranges. An integrated voltage reference eases design 1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. considerations. A duty cycle stabilizer (DCS) is provided to 2. Fast overrange and threshold detect. compensate for variations in the ADC clock duty cycle, 3. Proprietary differential input maintains excel ent SNR al owing the converters to maintain excellent performance. performance for input frequencies of up to 400 MHz. The ADC output data is routed directly to the two external 12-bit 4. SYNC input al ows synchronization of multiple devices. LVDS output ports and formatted as either interleaved or channel 5. 3-pin, 1.8 V SPI port for register programming and register multiplexed. readback. Flexible power-down options allow significant power savings, 6. Pin compatibility with the AD9643, allowing a simple when desired. migration up to 14 bits, and with the AD6649 and the AD6643.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE