Datasheet AD9613 (Analog Devices) - 2

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Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
EVALUATION KITS
• AN-282: Fundamentals of Sampled Data Systems • AD9613 Evaluation Board • AN-345: Grounding for Low-and-High-Frequency Circuits • AD9643 Evaluation Board • AN-501: Aperture Uncertainty and ADC System Performance • AN-586: LVDS Outputs for High Speed A/D Converters • AN-737: How ADIsimADC Models an ADC • AN-741: Little Known Characteristics of Phase Noise • AN-742: Frequency Domain Response of Switched- Capacitor ADCs • AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter • AN-807: Multicarrier WCDMA Feasibility • AN-808: Multicarrier CDMA2000 Feasibility • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs • AN-835: Understanding High Speed ADC Testing and Evaluation • AN-851: A WiMax Double Downconversion IF Sampling Receiver Design • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual • AN-935: Designing an ADC Transformer-Coupled Front End
Data Sheet
• AD9613: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet
Technical Books
• The Data Conversion Handbook, 2005
User Guides
• UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters
TOOLS AND SIMULATIONS
• Visual Analog • AD9613 IBIS Model Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE