Datasheet AD9643 (Analog Devices) - 8

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AD9643 Data Sheet SWITCHING SPECIFICATIONS Table 4. AD9643- 170 AD9643- 210 AD9643- 250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 40 170 40 210 40 250 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Full 0.8 0.8 0.8 ns Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (tPD) Full 6.0 6.0 6.0 ns DCO Propagation Delay (tDCO) Full 6.7 6.7 6.7 ns DCO-to-Data Skew (tSKEW) Full 0.4 0.7 1.0 0.4 0.7 1.0 0.4 0.7 1.0 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 10 µs Wake-Up Time (from Power-Down) Full 250 250 250 µs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider. Rev. E | Page 8 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide