Datasheet AD9643 (Analog Devices)

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9643 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 70.6 dBFS at 185 MHz A AVDD AGND DRVDD IN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and VIN+A PIPELINE D0± 250 MSPS 14-BIT 14 . VIN–A ADC . Total power consumption: 785 mW at 250 MSPS . VCM AD9643 PARALLEL . 1.8 V supply voltages DDR LVDS . VIN+B PIPELINE AND LVDS (ANSI-644 levels) outputs D13± 14-BIT 14 DRIVERS VIN–B ADC Integer 1-to-8 input clock divider (625 MHz maximum input) DCO± Sample rates of up to 250 MSPS REFERENCE IF sampling frequencies of up to 400 MHz OR± Internal ADC voltage reference 1 TO 8 Flexible analog input range SERIAL PORT CLOCK OEB 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) DIVIDER PDWN ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk SCLK SDIO CSB CLK+ CLK– SYNC Serial port control NOTES
001
Energy saving power-down modes 1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A AND CHANNE L B LVDS OUTPUT DATA.
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APPLICATIONS
Figure 1.
Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION
Programming for setup and control are accomplished using a The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) 3-wire SPI-compatible serial interface. with sampling speeds of up to 250 MSPS. The AD9643 is designed The AD9643 is available in a 64-lead LFCSP and is specified over to support communications applications, where low cost, smal the industrial temperature range of −40°C to +85°C. This size, wide bandwidth, and versatility are desired. product is protected by a U.S. patent. The dual ADC cores feature a multistage, differential pipelined
PRODUCT HIGHLIGHTS
architecture with integrated output error correction logic. Each 1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. ADC features wide bandwidth inputs supporting a variety of 2. Operation from a single 1.8 V supply and a separate digital user-selectable input ranges. An integrated voltage reference output driver supply accommodating LVDS outputs. eases design considerations. A duty cycle stabilizer is provided 3. Proprietary differential input maintains excellent SNR to compensate for variations in the ADC clock duty cycle, performance for input frequencies of up to 400 MHz. allowing the converters to maintain excellent performance. 4. SYNC input allows synchronization of multiple devices. The ADC output data is routed directly to the two external 5. 3-pin, 1.8 V SPI port for register programming and register 14-bit LVDS output ports and formatted as either interleaved or readback. channel multiplexed. 6. Pin compatibility with the AD9613, allowing a simple Flexible power-down options allow significant power savings, migration down from 14 bits to 12 bits. This part is also pin when desired. compatible with the AD6649 and the AD6643.
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Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide