Datasheet AD9643 (Analog Devices) - 7

FabricanteAnalog Devices
Descripción14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Páginas / Página36 / 7 — Data Sheet. AD9643. Parameter. Temp. Min. Typ. Max. Unit
RevisiónF
Formato / tamaño de archivoPDF / 1.2 Mb
Idioma del documentoInglés

Data Sheet. AD9643. Parameter. Temp. Min. Typ. Max. Unit

Data Sheet AD9643 Parameter Temp Min Typ Max Unit

Línea de modelo para esta hoja de datos

Versión de texto del documento

Data Sheet AD9643 Parameter Temp Min Typ Max Unit
DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), Full 1.15 1.22 1.35 V ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Full 1.15 1.22 1.35 V Reduced Swing Mode 1 Pull-up. 2 Pull-down. Rev. E | Page 7 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide