Datasheet AD9655 (Analog Devices) - 9

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AD9655 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted.
Table 6. Parameter1, 2 Temperature Min Typ Max Unit
CLOCK3 Input Clock Rate Full 20 1000 MHz Conversion Rate Full 20 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD)4 Full (tSAMPLE/4) + 5 (tSAMPLE/4) + 6.1 (tSAMPLE/4) + 7 ns Rise Time (tR)5 (20% to 80%) Full 170 ps Fall Time (tF)5 (20% to 80%) Full 160 ps FCO Propagation Delay (tFCO)4 Full (tSAMPLE/4) + 5 (tSAMPLE/4) + 6.1 (tSAMPLE/4) + 7 ns DCO Propagation Delay (tCPD) 4 Full tFCO + (tSAMPLE/16) + 0.2 ns DCO to Data Delay (tDATA) 4, 6 Full (tSAMPLE/16) − 500 (tSAMPLE/16) + 100 ps FCO to DCO Delay (tFRAME) 4, 7 Full (tSAMPLE/16) + 10 (tSAMPLE/16) + 330 ps Data to Data Skew Full ±37 ±80 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)8 25°C 250 ms Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA)9 25°C 1 ns Aperture Uncertainty (Jitter, t 5, 9 J ) 25°C 80 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 The Output parameters can be adjusted via the SPI. The conversion rate is the clock rate after the divider. Valid for 2-lane operation. 4 tSAMPLE = tEH + tEL = 1/fS. tCPD, tDATA and tFRAME are adjustable with SPI Register 0x16. 5 This term does not appear in the Timing Diagrams section, which includes Figure 2 and Figure 3. 6 tDATA is the time from DCO rise or fall to output data rise or fall. 7 tFRAME is the time from FCO rise to DCO rise. 8 Wake-up time from power-down is defined as the time required to return to normal operation from SPI power-down mode. The value of 250 ms assumes a sample rate of 125 MSPS. About 31 × 106 sample clock cycles are required. 9 tA and tJ are with Register 0x09 = 0x04 (default, duty cycle stabilizer and clock divider are bypassed).
TIMING SPECIFICATIONS Table 7. Parameter Description Limit Unit
SPI TIMING REQUIREMENTS See Figure 68, unless otherwise noted tDS Setup time between the data and the rising edge of SCLK 4 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min t 1 EN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the 10 ns min SCLK falling edge t 1 DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the 10 ns min SCLK rising edge 1 This parameter is not shown in Figure 68. Rev. 0 | Page 8 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE