Datasheet AD9655 (Analog Devices) - 8

Data Sheet AD9655 DIGITAL SPECIFICATIONS
AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted.
Table 5. Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS (SCLK/DFS) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (SDIO/PDWN) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF LOGIC OUTPUT (SDIO/PDWN)3 Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) Full ±298 ±350 ±400 mV Output Offset Voltage (VOS) Full 1.15 1.22 1.30 V Output Coding (Default) Twos complement DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (VOD) Full ±170 ±200 ±231 mV Output Offset Voltage (VOS) Full 1.15 1.22 1.30 V Output Coding (Default) Twos complement 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO/PDWN pins sharing the same connection. Rev. 0 | Page 7 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE