Datasheet AD9655 (Analog Devices)

Dual, 16-Bit, 125 MSPS Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9655 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation AVDD AGND DRVDD Low power: approximately 150 mW/channel at 125 MSPS, AD9655 2 V p-p input range (typical) D0A+ 16 D0A– SNR/SFDR at 69.5 MHz VINA+ 16-BIT D1A+ PIPELINE D1A– 77.5 dBFS/88 dBc, 2.0 V p-p input range (typical) VINA– ADC RS 16 E D0B+ R AND DDR 79.3 dBFS/84 dBc, 2.8 V p-p input range (typical) V VCM E D0B– 16 IZ DRI D1B+ Linearity VINB+ 16-BIT AL D1B– PIPELINE RI DS DNL = ±0.7 LSB; INL = ±4.0 LSB (typical, 2.0 V p-p input span) VINB– V ADC E DCO+ L 16 , S DCO– DNL = ±0.7 LSB; INL = ±3.4 LSB (typical, 2.8 V p-p input span) L L FCO+ P REFERENCE Serial LVDS, two data lanes per ADC channel FCO– 500 MHz full power analog bandwidth SERIAL PORT 1 TO 8 INTERFACE CLOCK DIVIDER Serial port control Full chip and individual channel power-down modes
001
SCLK/ SDIO/ CSB CLK+ CLK– DFS PDWN Flexible bit orientation
12737-
Built-in and custom digital test pattern generation
Figure 1.
Clock divider Programmable output clock and data alignment Standby mode APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications
Individual channel power-down is supported. The AD9655
Battery-powered instruments
typically consumes less than 2 mW in serial port interface (SPI)
Handheld scope meters
power-down mode. The available digital test pat-terns include
Portable medical imaging and ultrasound
built-in deterministic and pseudorandom patterns, along with
Radar/LIDAR
custom user-defined test patterns entered via the SPI.
GENERAL DESCRIPTION
The AD9655 is available in an RoHS-compliant, 32-lead LFCSP. The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital It is specified over the industrial temperature range of −40°C to converter (ADC) with an on-chip sample-and-hold circuit +85°C. This device is protected by a U.S. patent. designed for low cost, low power, small size, and ease of use.
PRODUCT HIGHLIGHTS
The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low 1. Small Footprint. Two ADCs are contained in a small, space-saving package. power in applications where a smal package size is critical. 2. Pin Compatible. The ADC requires a single 1.8 V power supply and an LVPECL-/ The AD9655 is pin compatible to the AD9645 14-bit and CMOS-/LVDS-compatible sample rate clock for full performance AD9635 12-bit dual ADCs. operation. External reference or driver components are not 3. Ease of Use. required for many applications. A DCO operates at frequencies of up to 500 MHz and The ADC automatically multiplies the sample rate clock for the supports double data rate (DDR) operation. appropriate LVDS serial data rate. A data clock output (DCO) 4. User Flexibility. for capturing data on the output and a frame clock output (FCO) The SPI control offers a wide range of flexible features to for signaling a new output byte are provided. meet specific system requirements.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE