Datasheet AD9684 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter |
| Páginas / Página | 65 / 8 — Data Sheet. AD9684. Parameter. Temperature. Min. Typ. Max. Unit. … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
Data Sheet. AD9684. Parameter. Temperature. Min. Typ. Max. Unit. SWITCHING SPECIFICATIONS. Table 4. Parameter
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Data Sheet AD9684 Parameter Temperature Min Typ Max Unit
DIGITAL OUTPUTS (Dx±,1 DCO±, STATUS±) Logic Compliance Full LVDS Differential Output Voltage Full 230 430 mV p-p Output Common-Mode Voltage (VCM) AC-Coupled 25°C 0 1.8 V Short-Circuit Current (IDSHORT) 25°C −100 +100 mA Differential Return Loss (RLDIFF)2 25°C 8 dB Common-Mode Return Loss (RLCM) 2 25°C 6 dB Differential Termination Impedance Full 80 100 120 Ω 1 Where x = 0 to 13. 2 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.7 V p-p ful -scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.25 4 GHz Maximum Sample Rate1 Full 500 MSPS Minimum Sample Rate2 Full 250 MSPS Clock Pulse Width High Full 1000 ps Low Full 1000 ps LVDS DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)3 Full 2.225 ns DCO± Propagation Delay (tDCO)3 Full 2.2 ns DCO± to Data Skew Rising Edge Data (tSKEWR)3 Full −150 −25 +100 ps Falling Edge Data (tSKEWF)3 Full 850 1.025 1100 ps STATUS± Propagation Delay (tSTATUS)4 Full 2.2 ns DCO± to STATUS± Skew (tFRAME)4 Full −150 −25 +100 ps Data Propagation Delay (tPD)3 Full 2.225 ns DCO± Propagation Delay (tDCO)3 Full 2.2 ns LATENCY5 Pipeline Latency Full 35 Clock cycles Fast Detect Latency Full 28 Clock cycles HB1 Filter Latency3 Full 50 Clock cycles HB1 + HB2 Filter Latency3 Full 101 Clock cycles HB1 + HB2 + HB3 Filter Latency3 Full 217 Clock cycles HB1 + HB2 + HB3 + HB4 Filter Latency3 Full 433 Clock cycles Fast Detect Latency Full 28 Clock cycles Wake-Up Time6 Standby 25°C 1 ms Power-Down 25°C 4 ms Rev. 0 | Page 7 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD9684 Parameter Temperature Min Typ Max Unit
DIGITAL OUTPUTS (Dx±,1 DCO±, STATUS±) Logic Compliance Full LVDS Differential Output Voltage Full 230 430 mV p-p Output Common-Mode Voltage (VCM) AC-Coupled 25°C 0 1.8 V Short-Circuit Current (IDSHORT) 25°C −100 +100 mA Differential Return Loss (RLDIFF)2 25°C 8 dB Common-Mode Return Loss (RLCM) 2 25°C 6 dB Differential Termination Impedance Full 80 100 120 Ω 1 Where x = 0 to 13. 2 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.7 V p-p ful -scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.25 4 GHz Maximum Sample Rate1 Full 500 MSPS Minimum Sample Rate2 Full 250 MSPS Clock Pulse Width High Full 1000 ps Low Full 1000 ps LVDS DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)3 Full 2.225 ns DCO± Propagation Delay (tDCO)3 Full 2.2 ns DCO± to Data Skew Rising Edge Data (tSKEWR)3 Full −150 −25 +100 ps Falling Edge Data (tSKEWF)3 Full 850 1.025 1100 ps STATUS± Propagation Delay (tSTATUS)4 Full 2.2 ns DCO± to STATUS± Skew (tFRAME)4 Full −150 −25 +100 ps Data Propagation Delay (tPD)3 Full 2.225 ns DCO± Propagation Delay (tDCO)3 Full 2.2 ns LATENCY5 Pipeline Latency Full 35 Clock cycles Fast Detect Latency Full 28 Clock cycles HB1 Filter Latency3 Full 50 Clock cycles HB1 + HB2 Filter Latency3 Full 101 Clock cycles HB1 + HB2 + HB3 Filter Latency3 Full 217 Clock cycles HB1 + HB2 + HB3 + HB4 Filter Latency3 Full 433 Clock cycles Fast Detect Latency Full 28 Clock cycles Wake-Up Time6 Standby 25°C 1 ms Power-Down 25°C 4 ms Rev. 0 | Page 7 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE