Datasheet AD9684 (Analog Devices)

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter Data Sheet AD9684 FEATURES FUNCTIONAL BLOCK DIAGRAM Parallel LVDS (DDR) outputs AVDD1 AVDD2 AVDD3 DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.8V TO 3.4V) 1.1 W total power per channel at 500 MSPS (default settings) BUFFER SFDR = 85 dBFS at 170 MHz fIN (500 MSPS) VIN+A ADC 14 D0± SNR = 68.6 dBFS at 170 MHz f CORE D1± IN (500 MSPS) VIN–A D2± DIGITAL D3± ENOB = 10.9 bits at 170 MHz f DOWN- IN D4± CONVERTER UT 16 D5± DNL = ±0.5 LSB FD_A P G D6± TS T CT E ITOR UT D7± NAL DS U GIN D8± T INL = ±2.5 LSB AS O V IG F ON L TP S TA D9± DE M DS S FD_B OU D10± V Noise density = −153 dBFS/Hz at 500 MSPS L D11± DIGITAL D12± DOWN- D13± 1.25 V, 2.50 V, and 3.3 V supply operation BUFFER CONVERTER DCO± VIN+B STATUS± No missing codes ADC 14 CORE CONTROL VIN–B Internal analog-to-digital converter (ADC) voltage reference REGISTERS FAST Flexible input range and termination impedance DETECT V_1P0 C L SIGNAL MONITOR SYNC+ 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) CLOCK SYN RO GENERATION S/ NT SYNC– 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential VD CLK+ L CO SYNC± input allows multichip synchronization SPI CONTROL CLK– ÷2 PDWN/ DDR LVDS (ANSI-644 levels) outputs ÷4 STBY AD9684 2 GHz usable analog input full power bandwidth ÷8
001
>96 dB channel isolation/crosstalk AGND DRGND DGND SDIO SCLK CSB
13015-
Amplitude detect bits for efficient AGC implementation
Figure 1.
Two integrated wideband digital processors per channel GENERAL DESCRIPTION 12-bit numerically controlled oscillator (NCO) 3 cascaded half-band filters
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has
Differential clock inputs
an on-chip buffer and a sample-and-hold circuit designed for
Serial port control
low power, small size, and ease of use. This product is designed
Integer clock divide by 2, 4, or 8
for sampling wide bandwidth analog signals. The AD9684 is
Small signal dither
optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a smal package.
APPLICATIONS
The dual ADC cores feature a multistage, differential pipelined
Communications
architecture with integrated output error correction logic. Each
Diversity multiband, multimode digital receivers
ADC features wide bandwidth buffered inputs, supporting a
3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE
variety of user selectable input ranges. An integrated voltage
General-purpose software radios
reference eases design considerations. Each ADC data output is
Ultrawideband satellite receiver
internal y connected to an optional decimate by 2 block.
Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
The analog input and clock signals are differential inputs. Each
Radar
ADC data output is internally connected to two digital
Digital oscilloscopes
downconverters (DDCs). Each DDC consists of four cascaded
High speed data acquisition systems
signal processing stages: a 12-bit frequency translator (NCO),
DOCSIS CMTS upstream receiver paths
and three half-band decimation filters supporting a divide by
HFC digital reverse path receivers
factor of two, four, and eight.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE