Datasheet AD9684 (Analog Devices) - 6

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Data Sheet AD9684 AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
ANALOG INPUT FULL SCALE Full 2.06 V p-p NOISE DENSITY2 Full −153 dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR)3 fIN = 10 MHz 25°C 69.2 dBFS fIN = 170 MHz Full 67.5 68.6 dBFS fIN = 340 MHz 25°C 68.4 dBFS fIN = 450 MHz 25°C 68.0 dBFS fIN = 765 MHz 25°C 64.4 dBFS fIN = 985 MHz 25°C 63.8 dBFS fIN = 1950 MHz 25°C 60.5 dBFS SIGNAL-TO-NOISE RATIO AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz 25°C 68.7 dBFS fIN = 170 MHz Full 67 68.5 dBFS fIN = 340 MHz 25°C 67.6 dBFS fIN = 450 MHz 25°C 67.2 dBFS fIN = 765 MHz 25°C 63.8 dBFS fIN = 985 MHz 25°C 62.5 dBFS fIN = 1950 MHz 25°C 58.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 11.1 Bits fIN = 170 MHz Full 10.8 10.9 Bits fIN = 340 MHz 25°C 10.8 Bits fIN = 450 MHz 25°C 10.8 Bits fIN = 765 MHz 25°C 10.3 Bits fIN = 985 MHz 25°C 10.1 Bits fIN = 1950 MHz 25°C 9.5 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz 25°C 83 dBFS fIN = 170 MHz Full 76 85 dBFS fIN = 340 MHz 25°C 82 dBFS fIN = 450 MHz 25°C 86 dBFS fIN = 765 MHz 25°C 81 dBFS fIN = 985 MHz 25°C 76 dBFS fIN = 1950 MHz 25°C 69 dBFS WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz 25°C −83 dBFS fIN = 170 MHz Full −85 −76 dBFS fIN = 340 MHz 25°C −82 dBFS fIN = 450 MHz 25°C −86 dBFS fIN = 765 MHz 25°C −81 dBFS fIN = 985 MHz 25°C −76 dBFS fIN = 1950 MHz 25°C −69 dBFS Rev. 0 | Page 5 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE